verilog代码实现的32位除以16位无符号整数除法器，在别人8位除法器的基础上改进完成，32个时钟周期完成一次运算。-verilog code for 32-bit divided by 16-bit unsigned integer divider　it s based on other guy s 8 bit divider verilog code. it need 32 clock cycles to complete an operation.