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文件名称:IIC-fpga-verilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2013-08-28
  • 文件大小：
    1.87mb
  • 已下载：
    0次
  • 提 供 者：
    n*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于fpga的IIC设计，verilog-IIC fpga-based design, verilog
(系统自动生成,下载前可以参看下载内容)

下载文件列表

IIC设计/i2c/i2c/bench/CVS/Entries
IIC设计/i2c/i2c/bench/CVS/Repository
IIC设计/i2c/i2c/bench/CVS/Root
IIC设计/i2c/i2c/bench/verilog/CVS/Entries
IIC设计/i2c/i2c/bench/verilog/CVS/Repository
IIC设计/i2c/i2c/bench/verilog/CVS/Root
IIC设计/i2c/i2c/bench/verilog/i2c_slave_model.v
IIC设计/i2c/i2c/bench/verilog/spi_slave_model.v
IIC设计/i2c/i2c/bench/verilog/tst_bench_top.v
IIC设计/i2c/i2c/bench/verilog/wb_master_model.v
IIC设计/i2c/i2c/CVS/Entries
IIC设计/i2c/i2c/CVS/Repository
IIC设计/i2c/i2c/CVS/Root
IIC设计/i2c/i2c/doc/CVS/Entries
IIC设计/i2c/i2c/doc/CVS/Repository
IIC设计/i2c/i2c/doc/CVS/Root
IIC设计/i2c/i2c/doc/i2c_specs.pdf
IIC设计/i2c/i2c/doc/src/CVS/Entries
IIC设计/i2c/i2c/doc/src/CVS/Repository
IIC设计/i2c/i2c/doc/src/CVS/Root
IIC设计/i2c/i2c/doc/src/I2C_specs.doc
IIC设计/i2c/i2c/documentation/CVS/Entries
IIC设计/i2c/i2c/documentation/CVS/Repository
IIC设计/i2c/i2c/documentation/CVS/Root
IIC设计/i2c/i2c/rtl/CVS/Entries
IIC设计/i2c/i2c/rtl/CVS/Repository
IIC设计/i2c/i2c/rtl/CVS/Root
IIC设计/i2c/i2c/rtl/verilog/CVS/Entries
IIC设计/i2c/i2c/rtl/verilog/CVS/Repository
IIC设计/i2c/i2c/rtl/verilog/CVS/Root
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.(0).cnf.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.(0).cnf.hdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.(1).cnf.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.(1).cnf.hdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.(2).cnf.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.(2).cnf.hdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.asm.qmsg
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.asm_labs.ddb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cbx.xml
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp.bpm
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp.ecobp
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp.hdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp.logdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp.rdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp.tdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp0.ddb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp2.ddb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp_bb.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp_bb.hdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp_bb.logdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.cmp_bb.rcf
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.dbp
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.db_info
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.eco.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.fit.qmsg
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.hier_info
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.hif
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.map.bpm
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.map.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.map.ecobp
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.map.hdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.map.logdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.map.qmsg
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.map_bb.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.map_bb.hdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.map_bb.logdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.pre_map.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.pre_map.hdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.psp
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.pss
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.rtlv.hdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.rtlv_sg.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.rtlv_sg_swap.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.sgdiff.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.sgdiff.hdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.signalprobe.cdb
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.sld_design_entry.sci
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.sld_design_entry_dsc.sci
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.smp_dump.txt
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.syn_hier_info
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.tan.qmsg
IIC设计/i2c/i2c/rtl/verilog/db/i2c_master_top.tis_db_list.ddb
IIC设计/i2c/i2c/rtl/verilog/i2c_master_bit_ctrl.v
IIC设计/i2c/i2c/rtl/verilog/i2c_master_byte_ctrl.v
IIC设计/i2c/i2c/rtl/verilog/i2c_master_defines.v
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.asm.rpt
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.done
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.fit.rpt
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.fit.smsg
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.fit.summary
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.flow.rpt
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.map.rpt
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.map.summary
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.pin
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.pof
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.qpf
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.qsf
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.qws
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.sof
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.tan.rpt
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.tan.summary
IIC设计/i2c/i2c/rtl/verilog/i2c_master_top.v
IIC设计/i2c/i2c/rtl/verilog/timescale.v
IIC设计/i2c/i2c/rtl/vhdl/CVS/Entries
IIC设计/i2c/i2c/rtl/vhdl/CVS/Repository
IIC设计/i2c/i2c/rtl/vhdl/CVS/Root
IIC设计/i2c/i2c/rtl/vhdl/I2C.VHD
IIC设计/i2c/i2c/rtl/vhdl/i2c_master

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