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文件名称:Tri-mode_Ethernet_MAC

  • 所属分类：
    Internet-Socket-Network
  • 标签属性：
    [PDF]
  • 上传时间：
    2013-09-04
  • 文件大小：
    1.1mb
  • 已下载：
    1次
  • 提 供 者：
    Dong****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

此包为三态以太网控制IP核，包内包含了仿真环境，说明文档，综合结果等文件。-This package is tri-mode Ethernet Controller IP core, the package contains a simulation environment, documentation, comprehensive results and other documents.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

bench/
bench/verilog/
bench/verilog/altera_mf.v
bench/verilog/host_sim.v
bench/verilog/Phy_sim.v
bench/verilog/reg_int_sim.v
bench/verilog/tb_top.v
bench/verilog/User_int_sim.v
doc/
doc/Tri-mode_Ethernet_MAC_Specifications.pdf
doc/Tri-mode_Ethernet_MAC_Verification_plan.pdf
EDK/
EDK/edk_user_repository.tar.gz
rtl/
rtl/verilog/
rtl/verilog/afifo.v
rtl/verilog/Clk_ctrl.v
rtl/verilog/eth_miim.v
rtl/verilog/header.v
rtl/verilog/MAC_rx/
rtl/verilog/MAC_rx/Broadcast_filter.v
rtl/verilog/MAC_rx/CRC_chk.v
rtl/verilog/MAC_rx/MAC_rx_add_chk.v
rtl/verilog/MAC_rx/MAC_rx_ctrl.v
rtl/verilog/MAC_rx/MAC_rx_FF.v
rtl/verilog/MAC_rx.v
rtl/verilog/MAC_top.v
rtl/verilog/MAC_tx/
rtl/verilog/MAC_tx/CRC_gen.v
rtl/verilog/MAC_tx/flow_ctrl.v
rtl/verilog/MAC_tx/MAC_tx_addr_add.v
rtl/verilog/MAC_tx/MAC_tx_Ctrl.v
rtl/verilog/MAC_tx/MAC_tx_FF.v
rtl/verilog/MAC_tx/Ramdon_gen.v
rtl/verilog/MAC_tx.v
rtl/verilog/miim/
rtl/verilog/miim/eth_clockgen.v
rtl/verilog/miim/eth_outputcontrol.v
rtl/verilog/miim/eth_shiftreg.v
rtl/verilog/miim/timescale.v
rtl/verilog/Phy_int.v
rtl/verilog/reg_int.v
rtl/verilog/RMON/
rtl/verilog/RMON/RMON_addr_gen.v
rtl/verilog/RMON/RMON_ctrl.v
rtl/verilog/RMON/RMON_dpram.v
rtl/verilog/RMON.v
rtl/verilog/TECH/
rtl/verilog/TECH/altera/
rtl/verilog/TECH/altera/CLK_DIV2.v
rtl/verilog/TECH/altera/CLK_SWITCH.v
rtl/verilog/TECH/altera/duram.v
rtl/verilog/TECH/CLK_DIV2.v
rtl/verilog/TECH/CLK_SWITCH.v
rtl/verilog/TECH/duram.v
rtl/verilog/TECH/xilinx/
rtl/verilog/TECH/xilinx/CLK_DIV2.v
rtl/verilog/TECH/xilinx/CLK_SWITCH.v
rtl/verilog/TECH/xilinx/duram.v
sim/
sim/rtl_sim/
sim/rtl_sim/modsim_sim/
sim/rtl_sim/modsim_sim/bin/
sim/rtl_sim/modsim_sim/bin/com.mod
sim/rtl_sim/modsim_sim/bin/ip_32W_check.dll
sim/rtl_sim/modsim_sim/bin/ip_32W_gen.dll
sim/rtl_sim/modsim_sim/bin/sim.mod
sim/rtl_sim/modsim_sim/bin/sim_only.mod
sim/rtl_sim/modsim_sim/bin/vlog-rtl.list
sim/rtl_sim/modsim_sim/data/
sim/rtl_sim/modsim_sim/data/1000Mbps_duplex.vec
sim/rtl_sim/modsim_sim/data/100Mbps_duplex.vec
sim/rtl_sim/modsim_sim/data/10Mbps_duplex.vec
sim/rtl_sim/modsim_sim/data/46-100.ini
sim/rtl_sim/modsim_sim/data/46-46.ini
sim/rtl_sim/modsim_sim/data/46-50.ini
sim/rtl_sim/modsim_sim/data/46-80.ini
sim/rtl_sim/modsim_sim/data/47-47.ini
sim/rtl_sim/modsim_sim/data/48-48.ini
sim/rtl_sim/modsim_sim/data/batch.dat
sim/rtl_sim/modsim_sim/data/config.ini
sim/rtl_sim/modsim_sim/data/CPU.vec
sim/rtl_sim/modsim_sim/data/flow_ctrl.vec
sim/rtl_sim/modsim_sim/data/source_mac_replace.vec
sim/rtl_sim/modsim_sim/data/target_mac_check.vec
sim/rtl_sim/modsim_sim/log/
sim/rtl_sim/modsim_sim/log/ncsim.log
sim/rtl_sim/modsim_sim/script/
sim/rtl_sim/modsim_sim/script/batch_mode.tcl
sim/rtl_sim/modsim_sim/script/filesel.tcl
sim/rtl_sim/modsim_sim/script/run.tcl
sim/rtl_sim/modsim_sim/script/run_proc.tcl
sim/rtl_sim/modsim_sim/script/set_reg_data.tcl
sim/rtl_sim/modsim_sim/script/set_stimulus.tcl
sim/rtl_sim/modsim_sim/script/start_verify.tcl
sim/rtl_sim/modsim_sim/script/user_lib.tcl
sim/rtl_sim/ncsim_sim/
sim/rtl_sim/ncsim_sim/bin/
sim/rtl_sim/ncsim_sim/bin/cds.lib
sim/rtl_sim/ncsim_sim/bin/com.nc
sim/rtl_sim/ncsim_sim/bin/config.ini
sim/rtl_sim/ncsim_sim/bin/hdl.var
sim/rtl_sim/ncsim_sim/bin/ip_32W_check.dll
sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll
sim/rtl_sim/ncsim_sim/bin/ip_32W_gen.dll
sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll
sim/rtl_sim/ncsim_sim/bin/sim.nc
sim/rtl_sim/ncsim_sim/bin/sim_only.nc
sim/rtl_sim/ncsim_sim/bin/vlog.list
sim/rtl_sim/ncsim_sim/data/
sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec
sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec
sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec
sim/rtl_sim/ncsim_sim/data/46-50.ini
sim/rtl_sim/ncsim_sim/data/batch.dat
sim/rtl_sim/ncsim_sim/data/config.ini
sim/rtl_sim/ncsim_sim/data/CPU.vec
sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec
sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec
sim/rtl_sim/ncsim_sim/data/target_mac_check.vec
sim/rtl_sim/ncsim_sim/log/
sim/rtl_sim/ncsim_sim/log/ncsim.log
sim/rtl_sim/ncsim_sim/script/
sim/rtl_sim/ncsim_sim/script/batch_mode.tcl
sim/rtl_sim/ncsim_sim/script/filesel.tcl
sim/rtl_sim/ncsim_sim/script/run.tcl
sim/rtl_sim/ncsim_sim/script/run_proc.tcl
sim/rtl_sim/ncsim_sim/script/set_reg_data.tcl
sim/rtl_sim/ncsim_sim/script/set_stimulus.tcl
sim/rtl_sim/ncsim_sim/script/start_verify.tcl
sim/rtl_sim/ncsim_sim/script/user_lib.tcl
syn/
syn/syn.prj
syn/syn_altrea.prj
syn/syn_xilinx.prj
start.tcl

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