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文件名称:MIPS-and-CPU-design-and-simulation

  • 所属分类：
    ARM-PowerPC-ColdFire-MIPS
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2013-09-13
  • 文件大小：
    2.23mb
  • 已下载：
    1次
  • 提 供 者：
    王***
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

兼容MIPS指令集的CPU设计与仿真

处理器架构为多周期，指令用32为字长（取指占一个周期），4k的存储器（指令存储器和数据存储器分开），IO与存储器统一编制，能支持20条指令以上-MIPS instruction set compatible CPU design and simulation
(系统自动生成,下载前可以参看下载内容)

下载文件列表

computer_design/design/110/123.cr.mti
computer_design/design/110/123.mpf
computer_design/design/110/memfile.dat
computer_design/design/110/mips.v
computer_design/design/110/mips.v.bak
computer_design/design/110/regfile.dat
computer_design/design/110/transcript
computer_design/design/110/vsim.wlf
computer_design/design/110/work/alu/verilog.asm
computer_design/design/110/work/alu/_primary.dat
computer_design/design/110/work/alu/_primary.vhd
computer_design/design/110/work/alucontrol/verilog.asm
computer_design/design/110/work/alucontrol/_primary.dat
computer_design/design/110/work/alucontrol/_primary.vhd
computer_design/design/110/work/controller/verilog.asm
computer_design/design/110/work/controller/_primary.dat
computer_design/design/110/work/controller/_primary.vhd
computer_design/design/110/work/datapath/verilog.asm
computer_design/design/110/work/datapath/_primary.dat
computer_design/design/110/work/datapath/_primary.vhd
computer_design/design/110/work/exmemory/verilog.asm
computer_design/design/110/work/exmemory/_primary.dat
computer_design/design/110/work/exmemory/_primary.vhd
computer_design/design/110/work/flop/verilog.asm
computer_design/design/110/work/flop/_primary.dat
computer_design/design/110/work/flop/_primary.vhd
computer_design/design/110/work/flopen/verilog.asm
computer_design/design/110/work/flopen/_primary.dat
computer_design/design/110/work/flopen/_primary.vhd
computer_design/design/110/work/flopenr/verilog.asm
computer_design/design/110/work/flopenr/_primary.dat
computer_design/design/110/work/flopenr/_primary.vhd
computer_design/design/110/work/mips/verilog.asm
computer_design/design/110/work/mips/_primary.dat
computer_design/design/110/work/mips/_primary.vhd
computer_design/design/110/work/mux2/verilog.asm
computer_design/design/110/work/mux2/_primary.dat
computer_design/design/110/work/mux2/_primary.vhd
computer_design/design/110/work/mux4/verilog.asm
computer_design/design/110/work/mux4/_primary.dat
computer_design/design/110/work/mux4/_primary.vhd
computer_design/design/110/work/regfile/verilog.asm
computer_design/design/110/work/regfile/_primary.dat
computer_design/design/110/work/regfile/_primary.vhd
computer_design/design/110/work/top/verilog.asm
computer_design/design/110/work/top/_primary.dat
computer_design/design/110/work/top/_primary.vhd
computer_design/design/110/work/zerodetect/verilog.asm
computer_design/design/110/work/zerodetect/_primary.dat
computer_design/design/110/work/zerodetect/_primary.vhd
computer_design/design/110/work/_info
computer_design/design/mips.v
computer_design/designbeq/110/123.cr.mti
computer_design/designbeq/110/123.mpf
computer_design/designbeq/110/memfile.dat
computer_design/designbeq/110/mips.v
computer_design/designbeq/110/mips.v.bak
computer_design/designbeq/110/regfile.dat
computer_design/designbeq/110/transcript
computer_design/designbeq/110/vsim.wlf
computer_design/designbeq/110/work/alu/verilog.asm
computer_design/designbeq/110/work/alu/_primary.dat
computer_design/designbeq/110/work/alu/_primary.vhd
computer_design/designbeq/110/work/alucontrol/verilog.asm
computer_design/designbeq/110/work/alucontrol/_primary.dat
computer_design/designbeq/110/work/alucontrol/_primary.vhd
computer_design/designbeq/110/work/controller/verilog.asm
computer_design/designbeq/110/work/controller/_primary.dat
computer_design/designbeq/110/work/controller/_primary.vhd
computer_design/designbeq/110/work/datapath/verilog.asm
computer_design/designbeq/110/work/datapath/_primary.dat
computer_design/designbeq/110/work/datapath/_primary.vhd
computer_design/designbeq/110/work/exmemory/verilog.asm
computer_design/designbeq/110/work/exmemory/_primary.dat
computer_design/designbeq/110/work/exmemory/_primary.vhd
computer_design/designbeq/110/work/flop/verilog.asm
computer_design/designbeq/110/work/flop/_primary.dat
computer_design/designbeq/110/work/flop/_primary.vhd
computer_design/designbeq/110/work/flopen/verilog.asm
computer_design/designbeq/110/work/flopen/_primary.dat
computer_design/designbeq/110/work/flopen/_primary.vhd
computer_design/designbeq/110/work/flopenr/verilog.asm
computer_design/designbeq/110/work/flopenr/_primary.dat
computer_design/designbeq/110/work/flopenr/_primary.vhd
computer_design/designbeq/110/work/mips/verilog.asm
computer_design/designbeq/110/work/mips/_primary.dat
computer_design/designbeq/110/work/mips/_primary.vhd
computer_design/designbeq/110/work/mux2/verilog.asm
computer_design/designbeq/110/work/mux2/_primary.dat
computer_design/designbeq/110/work/mux2/_primary.vhd
computer_design/designbeq/110/work/mux4/verilog.asm
computer_design/designbeq/110/work/mux4/_primary.dat
computer_design/designbeq/110/work/mux4/_primary.vhd
computer_design/designbeq/110/work/regfile/verilog.asm
computer_design/designbeq/110/work/regfile/_primary.dat
computer_design/designbeq/110/work/regfile/_primary.vhd
computer_design/designbeq/110/work/top/verilog.asm
computer_design/designbeq/110/work/top/_primary.dat
computer_design/designbeq/110/work/top/_primary.vhd
computer_design/designbeq/110/work/zerodetect/verilog.asm
computer_design/designbeq/110/work/zerodetect/_primary.dat
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