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文件名称:LFSR28_AWGN

  • 所属分类：
    Modem program
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-09-16
  • 文件大小：
    92.72kb
  • 已下载：
    0次
  • 提 供 者：
    何***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

高斯白噪声的产生完整程序，通过M序列叠加来产生。-To produce a complete program, white gaussian noise produced by superposition of M sequence.


(系统自动生成,下载前可以参看下载内容)

下载文件列表

LFSR28_AWGN/AWGN_GEN.v
LFSR28_AWGN/LFSR1.v
LFSR28_AWGN/LFSR10.v
LFSR28_AWGN/LFSR11.v
LFSR28_AWGN/LFSR12.v
LFSR28_AWGN/LFSR2.v
LFSR28_AWGN/LFSR28_AWGN.cr.mti
LFSR28_AWGN/LFSR28_AWGN.mpf
LFSR28_AWGN/LFSR3.v
LFSR28_AWGN/LFSR4.v
LFSR28_AWGN/LFSR5.v
LFSR28_AWGN/LFSR6.v
LFSR28_AWGN/LFSR7.v
LFSR28_AWGN/LFSR8.v
LFSR28_AWGN/LFSR9.v
LFSR28_AWGN/LFSR_AWGN.v
LFSR28_AWGN/work/@l@f@s@r1/verilog.prw
LFSR28_AWGN/work/@l@f@s@r1/verilog.psm
LFSR28_AWGN/work/@l@f@s@r1/_primary.dat
LFSR28_AWGN/work/@l@f@s@r1/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r1/_primary.vhd
LFSR28_AWGN/work/@l@f@s@r10/verilog.prw
LFSR28_AWGN/work/@l@f@s@r10/verilog.psm
LFSR28_AWGN/work/@l@f@s@r10/_primary.dat
LFSR28_AWGN/work/@l@f@s@r10/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r10/_primary.vhd
LFSR28_AWGN/work/@l@f@s@r11/verilog.prw
LFSR28_AWGN/work/@l@f@s@r11/verilog.psm
LFSR28_AWGN/work/@l@f@s@r11/_primary.dat
LFSR28_AWGN/work/@l@f@s@r11/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r11/_primary.vhd
LFSR28_AWGN/work/@l@f@s@r12/verilog.prw
LFSR28_AWGN/work/@l@f@s@r12/verilog.psm
LFSR28_AWGN/work/@l@f@s@r12/_primary.dat
LFSR28_AWGN/work/@l@f@s@r12/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r12/_primary.vhd
LFSR28_AWGN/work/@l@f@s@r2/verilog.prw
LFSR28_AWGN/work/@l@f@s@r2/verilog.psm
LFSR28_AWGN/work/@l@f@s@r2/_primary.dat
LFSR28_AWGN/work/@l@f@s@r2/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r2/_primary.vhd
LFSR28_AWGN/work/@l@f@s@r3/verilog.prw
LFSR28_AWGN/work/@l@f@s@r3/verilog.psm
LFSR28_AWGN/work/@l@f@s@r3/_primary.dat
LFSR28_AWGN/work/@l@f@s@r3/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r3/_primary.vhd
LFSR28_AWGN/work/@l@f@s@r4/verilog.prw
LFSR28_AWGN/work/@l@f@s@r4/verilog.psm
LFSR28_AWGN/work/@l@f@s@r4/_primary.dat
LFSR28_AWGN/work/@l@f@s@r4/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r4/_primary.vhd
LFSR28_AWGN/work/@l@f@s@r5/verilog.prw
LFSR28_AWGN/work/@l@f@s@r5/verilog.psm
LFSR28_AWGN/work/@l@f@s@r5/_primary.dat
LFSR28_AWGN/work/@l@f@s@r5/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r5/_primary.vhd
LFSR28_AWGN/work/@l@f@s@r6/verilog.prw
LFSR28_AWGN/work/@l@f@s@r6/verilog.psm
LFSR28_AWGN/work/@l@f@s@r6/_primary.dat
LFSR28_AWGN/work/@l@f@s@r6/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r6/_primary.vhd
LFSR28_AWGN/work/@l@f@s@r7/verilog.prw
LFSR28_AWGN/work/@l@f@s@r7/verilog.psm
LFSR28_AWGN/work/@l@f@s@r7/_primary.dat
LFSR28_AWGN/work/@l@f@s@r7/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r7/_primary.vhd
LFSR28_AWGN/work/@l@f@s@r8/verilog.prw
LFSR28_AWGN/work/@l@f@s@r8/verilog.psm
LFSR28_AWGN/work/@l@f@s@r8/_primary.dat
LFSR28_AWGN/work/@l@f@s@r8/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r8/_primary.vhd
LFSR28_AWGN/work/@l@f@s@r9/verilog.prw
LFSR28_AWGN/work/@l@f@s@r9/verilog.psm
LFSR28_AWGN/work/@l@f@s@r9/_primary.dat
LFSR28_AWGN/work/@l@f@s@r9/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r9/_primary.vhd
LFSR28_AWGN/work/@l@f@s@r_@a@w@g@n/verilog.prw
LFSR28_AWGN/work/@l@f@s@r_@a@w@g@n/verilog.psm
LFSR28_AWGN/work/@l@f@s@r_@a@w@g@n/_primary.dat
LFSR28_AWGN/work/@l@f@s@r_@a@w@g@n/_primary.dbs
LFSR28_AWGN/work/@l@f@s@r_@a@w@g@n/_primary.vhd
LFSR28_AWGN/work/awgn_gen/verilog.prw
LFSR28_AWGN/work/awgn_gen/verilog.psm
LFSR28_AWGN/work/awgn_gen/_primary.dat
LFSR28_AWGN/work/awgn_gen/_primary.dbs
LFSR28_AWGN/work/awgn_gen/_primary.vhd
LFSR28_AWGN/work/_info
LFSR28_AWGN/work/_vmake
LFSR28_AWGN/work/@l@f@s@r1
LFSR28_AWGN/work/@l@f@s@r10
LFSR28_AWGN/work/@l@f@s@r11
LFSR28_AWGN/work/@l@f@s@r12
LFSR28_AWGN/work/@l@f@s@r2
LFSR28_AWGN/work/@l@f@s@r3
LFSR28_AWGN/work/@l@f@s@r4
LFSR28_AWGN/work/@l@f@s@r5
LFSR28_AWGN/work/@l@f@s@r6
LFSR28_AWGN/work/@l@f@s@r7
LFSR28_AWGN/work/@l@f@s@r8
LFSR28_AWGN/work/@l@f@s@r9
LFSR28_AWGN/work/@l@f@s@r_@a@w@g@n
LFSR28_AWGN/work/awgn_gen
LFSR28_AWGN/work/_temp
LFSR28_AWGN/work
LFSR28_AWGN

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