文件名称:verilogsourcefiles
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- 上传时间:2008-10-13
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文件大小:19.74kb
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该代码中有不少关于学习verilog HDL的例子,对初学者有帮助
(系统自动生成,下载前可以参看下载内容)
下载文件列表
source files
source files/string.v
source files/half_adder.v
source files/audio_dac.v
source files/arith_test.v
source files/read_mem.v.bak
source files/task_example.v
source files/task_example.v.bak
source files/logical_test.v
source files/relat_test.v
source files/equal_test.v
source files/bit_test.v
source files/reduct_test.v
source files/shift_test.v
source files/mux_2_1.v.bak
source files/my_dff.v
source files/my_dff.v.bak
source files/mux_2_1.v
source files/fff2.v
source files/connect_test.v
source files/fff1.v
source files/fff2.v.bak
source files/testmemory.v
source files/testmemory.v.bak
source files/ex1.v
source files/transcript
source files/mytest.v
source files/mytest.v.bak
source files/ex2.v
source files/ex2.v.bak
source files/ex3.v
source files/ex3.v.bak
source files/ex4.v
source files/ex4.v.bak
source files/unknown.v
source files/unknown.v.bak
source files/about_time.v
source files/traffic_lights.v
source files/random_function.v
source files/random_function.v.bak
source files/mux4_1.v
source files/mux4_1.v.bak
source files/my_carry.v
source files/my_carry.v.bak
source files/my_sum.v
source files/adder_test.v
source files/traffic_lights.v.bak
source files/register_initialize.v
source files/register_initialize.v.bak
source files/demo_multiout_function.v
source files/shift_register_3.v
source files/shift_register_3.v.bak
source files/clk_counter.v
source files/demo_multiout_function.v.bak
source files/clk_counter_test.v
source files/clk_counter.v.bak
source files/clk_counter_test.v.bak
source files/8shift_register.v
source files/8shift_register.v.bak
source files/level_and_edge_sensitive_compare.v
source files/level_and_edge_sensitive_compare.v.bak
source files/timing_control_inner_mode.v.bak
source files/timing_control_inner_mode.v
source files/full_adder_1.v
source files/full_adder_1.v.bak
source files/dff.bak
source files/dff_asychronous.v
source files/ex1.v.bak
source files/clk_gen.v
source files/clk_gen.v.bak
source files/clk_gen1.v
source files/clk_gen1.v.bak
source files/counter.v
source files/counter.v.bak
source files/counter1.v
source files/counter1.v.bak
source files/8bits_multiplier.v
source files/8bits_multiplier.v.bak
source files/_8bits_multiplier1.v
source files/_8bits_multiplier1.v.bak
source files/left_shifter_4.v
source files/left_shifter_4.v.bak
www.dssz.com.txt
source files/string.v
source files/half_adder.v
source files/audio_dac.v
source files/arith_test.v
source files/read_mem.v.bak
source files/task_example.v
source files/task_example.v.bak
source files/logical_test.v
source files/relat_test.v
source files/equal_test.v
source files/bit_test.v
source files/reduct_test.v
source files/shift_test.v
source files/mux_2_1.v.bak
source files/my_dff.v
source files/my_dff.v.bak
source files/mux_2_1.v
source files/fff2.v
source files/connect_test.v
source files/fff1.v
source files/fff2.v.bak
source files/testmemory.v
source files/testmemory.v.bak
source files/ex1.v
source files/transcript
source files/mytest.v
source files/mytest.v.bak
source files/ex2.v
source files/ex2.v.bak
source files/ex3.v
source files/ex3.v.bak
source files/ex4.v
source files/ex4.v.bak
source files/unknown.v
source files/unknown.v.bak
source files/about_time.v
source files/traffic_lights.v
source files/random_function.v
source files/random_function.v.bak
source files/mux4_1.v
source files/mux4_1.v.bak
source files/my_carry.v
source files/my_carry.v.bak
source files/my_sum.v
source files/adder_test.v
source files/traffic_lights.v.bak
source files/register_initialize.v
source files/register_initialize.v.bak
source files/demo_multiout_function.v
source files/shift_register_3.v
source files/shift_register_3.v.bak
source files/clk_counter.v
source files/demo_multiout_function.v.bak
source files/clk_counter_test.v
source files/clk_counter.v.bak
source files/clk_counter_test.v.bak
source files/8shift_register.v
source files/8shift_register.v.bak
source files/level_and_edge_sensitive_compare.v
source files/level_and_edge_sensitive_compare.v.bak
source files/timing_control_inner_mode.v.bak
source files/timing_control_inner_mode.v
source files/full_adder_1.v
source files/full_adder_1.v.bak
source files/dff.bak
source files/dff_asychronous.v
source files/ex1.v.bak
source files/clk_gen.v
source files/clk_gen.v.bak
source files/clk_gen1.v
source files/clk_gen1.v.bak
source files/counter.v
source files/counter.v.bak
source files/counter1.v
source files/counter1.v.bak
source files/8bits_multiplier.v
source files/8bits_multiplier.v.bak
source files/_8bits_multiplier1.v
source files/_8bits_multiplier1.v.bak
source files/left_shifter_4.v
source files/left_shifter_4.v.bak
www.dssz.com.txt
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