文件名称:shiyan5
介绍说明--下载内容来自于网络,使用问题请自行百度
开发环境:unSP IDE 2.0.0
实验目的:
1)了解SPCE061A串行口(UART)的结构、与PC机串行通讯的原理。
2)了解UART的各配置单元P_UART_BaudScalarLow (7024H)、P_UART_BaudScalarHigh (7025H)、 P_UART_Command1(7021H)和P_UART_Command2 (7022H)的功能及控制方法。
3)掌握PC机与单片机通讯的编程方法。
实验设备:
1) 装有µ ’nSP™ IDE仿真环境的PC机一台。
2) µ ’nSP™ 十六位单片机实验箱一个。
3)连接软条线一根。
实验原理:
UART模块提供了一个全双工标准接口,用于完成SPCE061A与外设之间的串行通讯。借助于IOB口的特殊功能和UART IRQ中断,可以同时完成UART接口的接收发送数据的过程。 硬件电路原理为:使用一根连接软条线就可以实现串口自环测试。
实验步骤:
1)根据内容自行设计硬件连接图,连接硬件并检查。
2)画流程图并编写程序代码。
3)编译程序,软件调试。
4)观察LED、各个寄存器状态。
要求:
在从内存中能观测到发送和接收的数据。
(综合要求:按不同的键时向 PC发送不同内容的字符串。)
-The experiment:
1) Understanding SPCE061A serial port (UART) structure, with the PC serial communication works.
2) understand the UART each hive P_UART_BaudScalarLow (7024H), P_UART_BaudScalarHigh (7025H), P_UART_Command1 (7021H) and P_UART_Command2 (7022H) functions and control methods.
3) control communication between PC and microcontroller programming methods.
Laboratory equipment:
1) with μ nSP ™ IDE emulation environment for PC machine.
2) μ nSP ™ 16 single-chip experiment box one.
3) Connect a flexible lines.
Experimental principle:
Module provides a full-duplex UART standard interface for complete SPCE061A with serial communication between peripherals. With special features and IOB port UART IRQ interrupt, UART interface can complete the process of transmission and reception of data. Hardware circuit principle: use a soft line connection can be achieved serial loopback testing.
Experimental procedure:
1) self-designed hardware based on the content connecti
实验目的:
1)了解SPCE061A串行口(UART)的结构、与PC机串行通讯的原理。
2)了解UART的各配置单元P_UART_BaudScalarLow (7024H)、P_UART_BaudScalarHigh (7025H)、 P_UART_Command1(7021H)和P_UART_Command2 (7022H)的功能及控制方法。
3)掌握PC机与单片机通讯的编程方法。
实验设备:
1) 装有µ ’nSP™ IDE仿真环境的PC机一台。
2) µ ’nSP™ 十六位单片机实验箱一个。
3)连接软条线一根。
实验原理:
UART模块提供了一个全双工标准接口,用于完成SPCE061A与外设之间的串行通讯。借助于IOB口的特殊功能和UART IRQ中断,可以同时完成UART接口的接收发送数据的过程。 硬件电路原理为:使用一根连接软条线就可以实现串口自环测试。
实验步骤:
1)根据内容自行设计硬件连接图,连接硬件并检查。
2)画流程图并编写程序代码。
3)编译程序,软件调试。
4)观察LED、各个寄存器状态。
要求:
在从内存中能观测到发送和接收的数据。
(综合要求:按不同的键时向 PC发送不同内容的字符串。)
-The experiment:
1) Understanding SPCE061A serial port (UART) structure, with the PC serial communication works.
2) understand the UART each hive P_UART_BaudScalarLow (7024H), P_UART_BaudScalarHigh (7025H), P_UART_Command1 (7021H) and P_UART_Command2 (7022H) functions and control methods.
3) control communication between PC and microcontroller programming methods.
Laboratory equipment:
1) with μ nSP ™ IDE emulation environment for PC machine.
2) μ nSP ™ 16 single-chip experiment box one.
3) Connect a flexible lines.
Experimental principle:
Module provides a full-duplex UART standard interface for complete SPCE061A with serial communication between peripherals. With special features and IOB port UART IRQ interrupt, UART interface can complete the process of transmission and reception of data. Hardware circuit principle: use a soft line connection can be achieved serial loopback testing.
Experimental procedure:
1) self-designed hardware based on the content connecti
(系统自动生成,下载前可以参看下载内容)
下载文件列表
shiyan5/hardware.h
shiyan5/hardware.inc
shiyan5/Makefile
shiyan5/Resource.asm
shiyan5/Resource.inc
shiyan5/shiyan5.h
shiyan5/shiyan5.lik
shiyan5/shiyan5.opt
shiyan5/shiyan5.rc
shiyan5/shiyan5.set
shiyan5/shiyan5.spj
shiyan5/SPCE061A.h
shiyan5/SPCE061A.inc
shiyan5/UART_PC.asm
shiyan5/Device.env
shiyan5/Debug/Resource.lst
shiyan5/Debug/Resource.obj
shiyan5/Debug/shiyan5.ary
shiyan5/Debug/shiyan5.map
shiyan5/Debug/shiyan5.S37
shiyan5/Debug/shiyan5.sbm
shiyan5/Debug/shiyan5.smy
shiyan5/Debug/shiyan5.sym
shiyan5/Debug/UART_PC.lst
shiyan5/Debug/UART_PC.obj
shiyan5/shiyan5.env
shiyan5/Debug
shiyan5
shiyan5/hardware.inc
shiyan5/Makefile
shiyan5/Resource.asm
shiyan5/Resource.inc
shiyan5/shiyan5.h
shiyan5/shiyan5.lik
shiyan5/shiyan5.opt
shiyan5/shiyan5.rc
shiyan5/shiyan5.set
shiyan5/shiyan5.spj
shiyan5/SPCE061A.h
shiyan5/SPCE061A.inc
shiyan5/UART_PC.asm
shiyan5/Device.env
shiyan5/Debug/Resource.lst
shiyan5/Debug/Resource.obj
shiyan5/Debug/shiyan5.ary
shiyan5/Debug/shiyan5.map
shiyan5/Debug/shiyan5.S37
shiyan5/Debug/shiyan5.sbm
shiyan5/Debug/shiyan5.smy
shiyan5/Debug/shiyan5.sym
shiyan5/Debug/UART_PC.lst
shiyan5/Debug/UART_PC.obj
shiyan5/shiyan5.env
shiyan5/Debug
shiyan5
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