文件名称:FPGA
介绍说明--下载内容来自于网络,使用问题请自行百度
verilog编写的QPSK发射机的FPGA部分,已经过验证,完全达到要求。调制矢量误差4%-QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ZhilingjiFPGA/.lso
ZhilingjiFPGA/AD9767.v
ZhilingjiFPGA/AD9857.COE
ZhilingjiFPGA/AD9857.prj
ZhilingjiFPGA/AD9857.stx
ZhilingjiFPGA/AD9857.v
ZhilingjiFPGA/AD9857.xst
ZhilingjiFPGA/ad9857_initial.mif
ZhilingjiFPGA/AD9857_SPI.prj
ZhilingjiFPGA/AD9857_SPI.stx
ZhilingjiFPGA/AD9857_SPI.v
ZhilingjiFPGA/AD9857_SPI.xst
ZhilingjiFPGA/auto_project.ipf
ZhilingjiFPGA/auto_project_1.ipf
ZhilingjiFPGA/coregen_xil_860_109.cgc
ZhilingjiFPGA/coregen_xil_860_109.cgp
ZhilingjiFPGA/dcm.bmm
ZhilingjiFPGA/dcm.tfi
ZhilingjiFPGA/dcm.v
ZhilingjiFPGA/dcm2.tfi
ZhilingjiFPGA/dcm2.v
ZhilingjiFPGA/dcm2_arwz.ucf
ZhilingjiFPGA/dcm_arwz.ucf
ZhilingjiFPGA/EVM5.cfi
ZhilingjiFPGA/EVM5.prm
ZhilingjiFPGA/EVM5.sig
ZhilingjiFPGA/firfilter.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_0.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_1.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_10.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_11.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_12.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_13.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_14.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_15.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_16.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_17.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_18.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_19.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_2.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_20.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_3.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_4.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_5.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_6.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_7.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_8.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_9.mif
ZhilingjiFPGA/firfilterfilt_decode_rom.mif
ZhilingjiFPGA/fuse.log
ZhilingjiFPGA/impact.xsl
ZhilingjiFPGA/impact_impact.xwbt
ZhilingjiFPGA/ipcore_dir/blk_mem_gen_ds512.pdf
ZhilingjiFPGA/ipcore_dir/blk_mem_gen_readme.txt
ZhilingjiFPGA/ipcore_dir/coregen.cgc
ZhilingjiFPGA/ipcore_dir/coregen.cgp
ZhilingjiFPGA/ipcore_dir/coregen.log
ZhilingjiFPGA/ipcore_dir/coregen.rsp
ZhilingjiFPGA/ipcore_dir/dcm.v
ZhilingjiFPGA/ipcore_dir/dcm.xaw
ZhilingjiFPGA/ipcore_dir/dcm2.v
ZhilingjiFPGA/ipcore_dir/dcm2.xaw
ZhilingjiFPGA/ipcore_dir/dcm2_arwz.ucf
ZhilingjiFPGA/ipcore_dir/dcm2_flist.txt
ZhilingjiFPGA/ipcore_dir/dcm2_readme.txt
ZhilingjiFPGA/ipcore_dir/dcm2_xmdf.tcl
ZhilingjiFPGA/ipcore_dir/dcm_arwz.ucf
ZhilingjiFPGA/ipcore_dir/dcm_flist.txt
ZhilingjiFPGA/ipcore_dir/dcm_readme.txt
ZhilingjiFPGA/ipcore_dir/dcm_xmdf.tcl
ZhilingjiFPGA/ipcore_dir/dist_mem_gen_ds322.pdf
ZhilingjiFPGA/ipcore_dir/dist_mem_gen_readme.txt
ZhilingjiFPGA/ipcore_dir/fifo_generator_readme.txt
ZhilingjiFPGA/ipcore_dir/fifo_generator_ug175.pdf
ZhilingjiFPGA/ipcore_dir/firfilter.asy
ZhilingjiFPGA/ipcore_dir/firfilter.gise
ZhilingjiFPGA/ipcore_dir/firfilter.mif
ZhilingjiFPGA/ipcore_dir/firfilter.ncf
ZhilingjiFPGA/ipcore_dir/firfilter.ngc
ZhilingjiFPGA/ipcore_dir/firfilter.sym
ZhilingjiFPGA/ipcore_dir/firfilter.v
ZhilingjiFPGA/ipcore_dir/firfilter.veo
ZhilingjiFPGA/ipcore_dir/firfilter.vhd
ZhilingjiFPGA/ipcore_dir/firfilter.vho
ZhilingjiFPGA/ipcore_dir/firfilter.xco
ZhilingjiFPGA/ipcore_dir/firfilter.xco.bak
ZhilingjiFPGA/ipcore_dir/firfilter.xise
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_0.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_1.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_10.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_11.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_12.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_13.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_14.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_15.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_16.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_17.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_18.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_19.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_2.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_20.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_3.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_4.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_5.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_6.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_7.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_8.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_9.mif
ZhilingjiFPGA/ipcore_dir/firfilterfilt_decode_rom.mif
ZhilingjiFPGA/ipcore_dir/firfilter_flist.txt
ZhilingjiFPGA/ipcore_dir/firfilter_readme.txt
ZhilingjiFPGA/ipcore_dir/firfilter_xmdf.tcl
ZhilingjiFPGA/ipcore_dir/IQ_fifo.asy
ZhilingjiFPGA/ipcore_dir/IQ_fifo.gise
ZhilingjiFPGA/ipcore_dir/IQ_fifo.ncf
ZhilingjiFPGA/ipcore_dir/IQ_fifo.ngc
ZhilingjiFPGA/ipcore_dir/IQ_fifo.sym
ZhilingjiFPGA/ipcore_dir/IQ_fifo.v
ZhilingjiFPGA/ipcore_dir/IQ_fifo.veo
ZhilingjiFPGA/ipcore_dir/IQ_fifo.vhd
ZhilingjiFPGA/ipcore_dir/IQ_fifo.vho
ZhilingjiFPGA/ipcore_dir/IQ_fifo.xco
ZhilingjiFPGA/ipcore_dir/IQ_fifo.xco.bak
ZhilingjiFPGA/ipcore_dir/IQ_fifo.xise
ZhilingjiFPGA/ipcore_dir/IQ_fifo_flist.txt
ZhilingjiFPGA/ipcore_dir/IQ_fifo_xmdf.tcl
ZhilingjiFPGA/ipcore_dir/MultiXY.asy
ZhilingjiFPGA/ipcore_dir/MultiXY.gise
ZhilingjiFPGA/ipcore_dir/MultiXY.ncf
ZhilingjiFPGA/ipcore_dir/MultiXY.ngc
ZhilingjiFPGA/ipcore_dir/MultiXY.sym
Zhili
ZhilingjiFPGA/AD9767.v
ZhilingjiFPGA/AD9857.COE
ZhilingjiFPGA/AD9857.prj
ZhilingjiFPGA/AD9857.stx
ZhilingjiFPGA/AD9857.v
ZhilingjiFPGA/AD9857.xst
ZhilingjiFPGA/ad9857_initial.mif
ZhilingjiFPGA/AD9857_SPI.prj
ZhilingjiFPGA/AD9857_SPI.stx
ZhilingjiFPGA/AD9857_SPI.v
ZhilingjiFPGA/AD9857_SPI.xst
ZhilingjiFPGA/auto_project.ipf
ZhilingjiFPGA/auto_project_1.ipf
ZhilingjiFPGA/coregen_xil_860_109.cgc
ZhilingjiFPGA/coregen_xil_860_109.cgp
ZhilingjiFPGA/dcm.bmm
ZhilingjiFPGA/dcm.tfi
ZhilingjiFPGA/dcm.v
ZhilingjiFPGA/dcm2.tfi
ZhilingjiFPGA/dcm2.v
ZhilingjiFPGA/dcm2_arwz.ucf
ZhilingjiFPGA/dcm_arwz.ucf
ZhilingjiFPGA/EVM5.cfi
ZhilingjiFPGA/EVM5.prm
ZhilingjiFPGA/EVM5.sig
ZhilingjiFPGA/firfilter.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_0.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_1.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_10.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_11.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_12.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_13.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_14.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_15.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_16.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_17.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_18.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_19.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_2.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_20.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_3.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_4.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_5.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_6.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_7.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_8.mif
ZhilingjiFPGA/firfilterCOEFF_auto0_9.mif
ZhilingjiFPGA/firfilterfilt_decode_rom.mif
ZhilingjiFPGA/fuse.log
ZhilingjiFPGA/impact.xsl
ZhilingjiFPGA/impact_impact.xwbt
ZhilingjiFPGA/ipcore_dir/blk_mem_gen_ds512.pdf
ZhilingjiFPGA/ipcore_dir/blk_mem_gen_readme.txt
ZhilingjiFPGA/ipcore_dir/coregen.cgc
ZhilingjiFPGA/ipcore_dir/coregen.cgp
ZhilingjiFPGA/ipcore_dir/coregen.log
ZhilingjiFPGA/ipcore_dir/coregen.rsp
ZhilingjiFPGA/ipcore_dir/dcm.v
ZhilingjiFPGA/ipcore_dir/dcm.xaw
ZhilingjiFPGA/ipcore_dir/dcm2.v
ZhilingjiFPGA/ipcore_dir/dcm2.xaw
ZhilingjiFPGA/ipcore_dir/dcm2_arwz.ucf
ZhilingjiFPGA/ipcore_dir/dcm2_flist.txt
ZhilingjiFPGA/ipcore_dir/dcm2_readme.txt
ZhilingjiFPGA/ipcore_dir/dcm2_xmdf.tcl
ZhilingjiFPGA/ipcore_dir/dcm_arwz.ucf
ZhilingjiFPGA/ipcore_dir/dcm_flist.txt
ZhilingjiFPGA/ipcore_dir/dcm_readme.txt
ZhilingjiFPGA/ipcore_dir/dcm_xmdf.tcl
ZhilingjiFPGA/ipcore_dir/dist_mem_gen_ds322.pdf
ZhilingjiFPGA/ipcore_dir/dist_mem_gen_readme.txt
ZhilingjiFPGA/ipcore_dir/fifo_generator_readme.txt
ZhilingjiFPGA/ipcore_dir/fifo_generator_ug175.pdf
ZhilingjiFPGA/ipcore_dir/firfilter.asy
ZhilingjiFPGA/ipcore_dir/firfilter.gise
ZhilingjiFPGA/ipcore_dir/firfilter.mif
ZhilingjiFPGA/ipcore_dir/firfilter.ncf
ZhilingjiFPGA/ipcore_dir/firfilter.ngc
ZhilingjiFPGA/ipcore_dir/firfilter.sym
ZhilingjiFPGA/ipcore_dir/firfilter.v
ZhilingjiFPGA/ipcore_dir/firfilter.veo
ZhilingjiFPGA/ipcore_dir/firfilter.vhd
ZhilingjiFPGA/ipcore_dir/firfilter.vho
ZhilingjiFPGA/ipcore_dir/firfilter.xco
ZhilingjiFPGA/ipcore_dir/firfilter.xco.bak
ZhilingjiFPGA/ipcore_dir/firfilter.xise
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_0.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_1.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_10.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_11.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_12.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_13.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_14.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_15.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_16.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_17.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_18.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_19.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_2.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_20.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_3.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_4.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_5.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_6.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_7.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_8.mif
ZhilingjiFPGA/ipcore_dir/firfilterCOEFF_auto0_9.mif
ZhilingjiFPGA/ipcore_dir/firfilterfilt_decode_rom.mif
ZhilingjiFPGA/ipcore_dir/firfilter_flist.txt
ZhilingjiFPGA/ipcore_dir/firfilter_readme.txt
ZhilingjiFPGA/ipcore_dir/firfilter_xmdf.tcl
ZhilingjiFPGA/ipcore_dir/IQ_fifo.asy
ZhilingjiFPGA/ipcore_dir/IQ_fifo.gise
ZhilingjiFPGA/ipcore_dir/IQ_fifo.ncf
ZhilingjiFPGA/ipcore_dir/IQ_fifo.ngc
ZhilingjiFPGA/ipcore_dir/IQ_fifo.sym
ZhilingjiFPGA/ipcore_dir/IQ_fifo.v
ZhilingjiFPGA/ipcore_dir/IQ_fifo.veo
ZhilingjiFPGA/ipcore_dir/IQ_fifo.vhd
ZhilingjiFPGA/ipcore_dir/IQ_fifo.vho
ZhilingjiFPGA/ipcore_dir/IQ_fifo.xco
ZhilingjiFPGA/ipcore_dir/IQ_fifo.xco.bak
ZhilingjiFPGA/ipcore_dir/IQ_fifo.xise
ZhilingjiFPGA/ipcore_dir/IQ_fifo_flist.txt
ZhilingjiFPGA/ipcore_dir/IQ_fifo_xmdf.tcl
ZhilingjiFPGA/ipcore_dir/MultiXY.asy
ZhilingjiFPGA/ipcore_dir/MultiXY.gise
ZhilingjiFPGA/ipcore_dir/MultiXY.ncf
ZhilingjiFPGA/ipcore_dir/MultiXY.ngc
ZhilingjiFPGA/ipcore_dir/MultiXY.sym
Zhili
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.