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文件名称:cpu

  • 所属分类：
    数据结构常用算法
  • 标签属性：
    [PDF]
  • 上传时间：
    2008-10-13
  • 文件大小：
    1.59mb
  • 已下载：
    0次
  • 提 供 者：
    gexi*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

本人制作的8位CPU,有简单的加减,输入,输出操作,希望大家好用
(系统自动生成,下载前可以参看下载内容)

下载文件列表

80386.zip
IT51_src[1].tar.gz
openrisc1200/or1k/or1200/CVS/Root
openrisc1200/or1k/or1200/CVS/Repository
openrisc1200/or1k/or1200/CVS/Entries
openrisc1200/or1k/or1200/CVS
openrisc1200/or1k/or1200/bench/CVS/Root
openrisc1200/or1k/or1200/bench/CVS/Repository
openrisc1200/or1k/or1200/bench/CVS/Entries
openrisc1200/or1k/or1200/bench/CVS
openrisc1200/or1k/or1200/bench/README
openrisc1200/or1k/or1200/bench
openrisc1200/or1k/or1200/doc/CVS/Root
openrisc1200/or1k/or1200/doc/CVS/Repository
openrisc1200/or1k/or1200/doc/CVS/Entries
openrisc1200/or1k/or1200/doc/CVS
openrisc1200/or1k/or1200/doc/or1200_spec.doc
openrisc1200/or1k/or1200/doc/or1200_spec.pdf
openrisc1200/or1k/or1200/doc
openrisc1200/or1k/or1200/lib/CVS/Root
openrisc1200/or1k/or1200/lib/CVS/Repository
openrisc1200/or1k/or1200/lib/CVS/Entries
openrisc1200/or1k/or1200/lib/CVS
openrisc1200/or1k/or1200/lib/README
openrisc1200/or1k/or1200/lib
openrisc1200/or1k/or1200/lint/CVS/Root
openrisc1200/or1k/or1200/lint/CVS/Repository
openrisc1200/or1k/or1200/lint/CVS/Entries
openrisc1200/or1k/or1200/lint/CVS
openrisc1200/or1k/or1200/lint/bin/CVS/Root
openrisc1200/or1k/or1200/lint/bin/CVS/Repository
openrisc1200/or1k/or1200/lint/bin/CVS/Entries
openrisc1200/or1k/or1200/lint/bin/CVS
openrisc1200/or1k/or1200/lint/bin/README
openrisc1200/or1k/or1200/lint/bin/run_lint
openrisc1200/or1k/or1200/lint/bin
openrisc1200/or1k/or1200/lint/log/CVS/Root
openrisc1200/or1k/or1200/lint/log/CVS/Repository
openrisc1200/or1k/or1200/lint/log/CVS/Entries
openrisc1200/or1k/or1200/lint/log/CVS
openrisc1200/or1k/or1200/lint/log/README
openrisc1200/or1k/or1200/lint/log
openrisc1200/or1k/or1200/lint/run/CVS/Root
openrisc1200/or1k/or1200/lint/run/CVS/Repository
openrisc1200/or1k/or1200/lint/run/CVS/Entries
openrisc1200/or1k/or1200/lint/run/CVS
openrisc1200/or1k/or1200/lint/run/README
openrisc1200/or1k/or1200/lint/run
openrisc1200/or1k/or1200/lint
openrisc1200/or1k/or1200/rtl/CVS/Root
openrisc1200/or1k/or1200/rtl/CVS/Repository
openrisc1200/or1k/or1200/rtl/CVS/Entries
openrisc1200/or1k/or1200/rtl/CVS
openrisc1200/or1k/or1200/rtl/verilog/CVS/Root
openrisc1200/or1k/or1200/rtl/verilog/CVS/Repository
openrisc1200/or1k/or1200/rtl/verilog/CVS/Entries
openrisc1200/or1k/or1200/rtl/verilog/CVS
openrisc1200/or1k/or1200/rtl/verilog/or1200_alu.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_amultp2_32x32.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_cfgr.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_cpu.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_ctrl.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_dc_fsm.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_dc_ram.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_dc_tag.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_dc_top.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_defines.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_dmmu_tlb.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_dmmu_top.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_dpram_256x32.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_dpram_32x32.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_du.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_except.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_freeze.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_genpc.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_gmultp2_32x32.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_ic_fsm.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_ic_ram.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_ic_tag.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_ic_top.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_if.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_immu_tlb.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_immu_top.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_iwb_biu.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_lsu.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_mem2reg.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_mult_mac.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_operandmuxes.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_pic.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_pm.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_qmem_top.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_reg2mem.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_rf.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_rfram_generic.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_sb.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_sb_fifo.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_1024x32.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_1024x8.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_128x32.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_2048x32.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_2048x8.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_256x21.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_32x24.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_512x20.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_64x14.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_64x22.v
openrisc1200/or1k/or1200/rtl/verilog/or1200_spram_64x24.v
openrisc1200/or1k/or1200/rtl/veril

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