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文件名称:ex1

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    2013-10-19
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    428.43kb
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设计一个循环灯控制器,该控制器控制红、绿、黄三个发光管循环发亮。要求红发光管亮2秒,绿发光管亮3秒,黄发光管亮1秒。(假设外部提供频率为1MHz的方波信号)



编程环境为Quartus II 11.0

仿真环境为 Modelsim 6.6d



通过仿真可以看出。系统复位后,红发光管亮2秒,绿发光管亮3秒,黄发光管亮1秒,三个发光管循环发亮。

-Design a loop lamp controller that controls the red, green and yellow three LED lights cycle. Requirements red LED light 2 seconds, the green LED light 3 seconds, yellow light-emitting tube light 1 second. (Assuming a frequency of 1MHz externally a square wave signal)



Programming environment for Quartus II 11.0

Simulation environment for the Modelsim 6.6d



The simulation can be seen. After a system reset, the red LED light 2 seconds, the green LED light 3 seconds, yellow light-emitting tube light 1 second, three LED lights cycle.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ex1/
ex1/db/
ex1/db/ex1.(0).cnf.cdb
ex1/db/ex1.(0).cnf.hdb
ex1/db/ex1.amm.cdb
ex1/db/ex1.asm.qmsg
ex1/db/ex1.asm.rdb
ex1/db/ex1.asm_labs.ddb
ex1/db/ex1.cbx.xml
ex1/db/ex1.cmp.bpm
ex1/db/ex1.cmp.cdb
ex1/db/ex1.cmp.hdb
ex1/db/ex1.cmp.kpt
ex1/db/ex1.cmp.logdb
ex1/db/ex1.cmp.rdb
ex1/db/ex1.cmp0.ddb
ex1/db/ex1.cmp1.ddb
ex1/db/ex1.cmp2.ddb
ex1/db/ex1.cmp_merge.kpt
ex1/db/ex1.db_info
ex1/db/ex1.eda.qmsg
ex1/db/ex1.fit.qmsg
ex1/db/ex1.hier_info
ex1/db/ex1.hif
ex1/db/ex1.idb.cdb
ex1/db/ex1.lpc.html
ex1/db/ex1.lpc.rdb
ex1/db/ex1.lpc.txt
ex1/db/ex1.map.bpm
ex1/db/ex1.map.cdb
ex1/db/ex1.map.hdb
ex1/db/ex1.map.kpt
ex1/db/ex1.map.logdb
ex1/db/ex1.map.qmsg
ex1/db/ex1.map_bb.cdb
ex1/db/ex1.map_bb.hdb
ex1/db/ex1.map_bb.logdb
ex1/db/ex1.pre_map.cdb
ex1/db/ex1.pre_map.hdb
ex1/db/ex1.rpp.qmsg
ex1/db/ex1.rtlv.hdb
ex1/db/ex1.rtlv_sg.cdb
ex1/db/ex1.rtlv_sg_swap.cdb
ex1/db/ex1.sgate.rvd
ex1/db/ex1.sgate_sm.rvd
ex1/db/ex1.sgdiff.cdb
ex1/db/ex1.sgdiff.hdb
ex1/db/ex1.sld_design_entry.sci
ex1/db/ex1.sld_design_entry_dsc.sci
ex1/db/ex1.smart_action.txt
ex1/db/ex1.sta.qmsg
ex1/db/ex1.sta.rdb
ex1/db/ex1.sta_cmp.8_slow.tdb
ex1/db/ex1.syn_hier_info
ex1/db/ex1.tis_db_list.ddb
ex1/db/logic_util_heursitic.dat
ex1/db/prev_cmp_ex1.qmsg
ex1/ex1.asm.rpt
ex1/ex1.done
ex1/ex1.eda.rpt
ex1/ex1.fit.rpt
ex1/ex1.fit.smsg
ex1/ex1.fit.summary
ex1/ex1.flow.rpt
ex1/ex1.map.rpt
ex1/ex1.map.summary
ex1/ex1.pin
ex1/ex1.pof
ex1/ex1.qpf
ex1/ex1.qsf
ex1/ex1.sof
ex1/ex1.sta.rpt
ex1/ex1.sta.summary
ex1/ex1.vhd
ex1/ex1.vhd.bak
ex1/ex1_nativelink_simulation.rpt
ex1/incremental_db/
ex1/incremental_db/README
ex1/incremental_db/compiled_partitions/
ex1/incremental_db/compiled_partitions/ex1.db_info
ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.cdb
ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.dfp
ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hdb
ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.kpt
ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.logdb
ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.rcfdb
ex1/incremental_db/compiled_partitions/ex1.root_partition.map.cdb
ex1/incremental_db/compiled_partitions/ex1.root_partition.map.dpi
ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.cdb
ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.hb_info
ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.hdb
ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.sig
ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hdb
ex1/incremental_db/compiled_partitions/ex1.root_partition.map.kpt
ex1/simulation/
ex1/simulation/modelsim/
ex1/simulation/modelsim/ex1.sft
ex1/simulation/modelsim/ex1.vho
ex1/simulation/modelsim/ex1.vht
ex1/simulation/modelsim/ex1.vht.bak
ex1/simulation/modelsim/ex1_fast.vho
ex1/simulation/modelsim/ex1_modelsim.xrf
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do.bak
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do.bak1
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do.bak10
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do.bak11
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do.bak2
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do.bak3
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do.bak4
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do.bak5
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do.bak6
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do.bak7
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do.bak8
ex1/simulation/modelsim/ex1_run_msim_rtl_vhdl.do.bak9
ex1/simulation/modelsim/ex1_vhd.sdo
ex1/simulation/modelsim/ex1_vhd_fast.sdo
ex1/simulation/modelsim/modelsim.ini
ex1/simulation/modelsim/msim_transcript
ex1/simulation/modelsim/rtl_work/
ex1/simulation/modelsim/rtl_work/_info
ex1/simulation/modelsim/rtl_work/_temp/
ex1/simulation/modelsim/rtl_work/_vmake
ex1/simulation/modelsim/rtl_work/ex1/
ex1/simulation/modelsim/rtl_work/ex1/_primary.dat
ex1/simulation/modelsim/rtl_work/ex1/_primary.dbs
ex1/simulation/modelsim/rtl_work/ex1/behav.dat
ex1/simulation/modelsim/rtl_work/ex1/behav.dbs
ex1/simulation/modelsim/rtl_work/ex1/behav.prw
ex1/simulation/modelsim/rtl_work/ex1/behav.psm
ex1/simulation/modelsim/rtl_work/ex1_vhd_tst/
ex1/simulation/modelsim/rtl_work/ex1_vhd_tst/_primary.dat
ex1/simulation/modelsim/rtl_work/ex1_vhd_tst/_primary.dbs
ex1/simulation/modelsim/vsim.wlf

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