文件名称:AD_DA
介绍说明--下载内容来自于网络,使用问题请自行百度
使用MATLAB工具,对信号进行采集调制,再进行信号解码.对信号进行算法控制.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
AD_DA/adctest.mdl
AD_DA/dac_test.err
AD_DA/dac_test.mdl
AD_DA/dac_test_black_box1_wrapper.v
AD_DA/dac_test_black_box_wrapper.v
AD_DA/fir_160_tap.v
AD_DA/fir_top.fsdb
AD_DA/fir_top.v
AD_DA/fir_top_config.m
AD_DA/fm_test.mdl
AD_DA/iir_6_filter.v
AD_DA/iir_filter.v
AD_DA/iir_filter_config.m
AD_DA/isimwavedata.xwv
AD_DA/rom.txt
AD_DA/sig_test.mdl
AD_DA/sysgenADCDAC.mdl
AD_DA/sysgenADCDAC_PreLoadFcn.m
AD_DA/test.fsdb
AD_DA/transcript
AD_DA/untitled.fda
AD_DA/xlcosim_dac_test_modelsim.tcl
AD_DA/xlcosim_dac_test_modelsim.vhd
AD_DA/xlcosim_dac_test_modelsimf.vhd
AD_DA/xlcosim_dac_test_modelsim_clk_drvr.vhd
AD_DA/work/_info
AD_DA/work/asr_ram/verilog.asm
AD_DA/work/asr_ram/_primary.dat
AD_DA/work/asr_ram/_primary.vhd
AD_DA/work/asr_ram
AD_DA/work/dac_test_black_box1_wrapper/verilog.asm
AD_DA/work/dac_test_black_box1_wrapper/_primary.dat
AD_DA/work/dac_test_black_box1_wrapper/_primary.vhd
AD_DA/work/dac_test_black_box1_wrapper
AD_DA/work/dac_test_black_box_wrapper/verilog.asm
AD_DA/work/dac_test_black_box_wrapper/_primary.dat
AD_DA/work/dac_test_black_box_wrapper/_primary.vhd
AD_DA/work/dac_test_black_box_wrapper
AD_DA/work/fir_160_tap/verilog.asm
AD_DA/work/fir_160_tap/_primary.dat
AD_DA/work/fir_160_tap/_primary.vhd
AD_DA/work/fir_160_tap
AD_DA/work/fir_asr/verilog.asm
AD_DA/work/fir_asr/_primary.dat
AD_DA/work/fir_asr/_primary.vhd
AD_DA/work/fir_asr
AD_DA/work/fir_mac/verilog.asm
AD_DA/work/fir_mac/_primary.dat
AD_DA/work/fir_mac/_primary.vhd
AD_DA/work/fir_mac
AD_DA/work/fir_rom/verilog.asm
AD_DA/work/fir_rom/_primary.dat
AD_DA/work/fir_rom/_primary.vhd
AD_DA/work/fir_rom
AD_DA/work/fir_top/verilog.asm
AD_DA/work/fir_top/_primary.dat
AD_DA/work/fir_top/_primary.vhd
AD_DA/work/fir_top
AD_DA/work/iir_6_filter/verilog.asm
AD_DA/work/iir_6_filter/_primary.dat
AD_DA/work/iir_6_filter/_primary.vhd
AD_DA/work/iir_6_filter
AD_DA/work/iir_filter/verilog.asm
AD_DA/work/iir_filter/_primary.dat
AD_DA/work/iir_filter/_primary.vhd
AD_DA/work/iir_filter
AD_DA/work/xlcosim_dac_test_modelsim/structural.asm
AD_DA/work/xlcosim_dac_test_modelsim/structural.dat
AD_DA/work/xlcosim_dac_test_modelsim/_primary.dat
AD_DA/work/xlcosim_dac_test_modelsim
AD_DA/work/xlcosim_dac_test_modelsim_clk_drvr/behavior.asm
AD_DA/work/xlcosim_dac_test_modelsim_clk_drvr/behavior.dat
AD_DA/work/xlcosim_dac_test_modelsim_clk_drvr/_primary.dat
AD_DA/work/xlcosim_dac_test_modelsim_clk_drvr
AD_DA/work/xlcosim_fli_controller/only.asm
AD_DA/work/xlcosim_fli_controller/only.dat
AD_DA/work/xlcosim_fli_controller/_primary.dat
AD_DA/work/xlcosim_fli_controller
AD_DA/work
AD_DA
www.dssz.com.txt
AD_DA/dac_test.err
AD_DA/dac_test.mdl
AD_DA/dac_test_black_box1_wrapper.v
AD_DA/dac_test_black_box_wrapper.v
AD_DA/fir_160_tap.v
AD_DA/fir_top.fsdb
AD_DA/fir_top.v
AD_DA/fir_top_config.m
AD_DA/fm_test.mdl
AD_DA/iir_6_filter.v
AD_DA/iir_filter.v
AD_DA/iir_filter_config.m
AD_DA/isimwavedata.xwv
AD_DA/rom.txt
AD_DA/sig_test.mdl
AD_DA/sysgenADCDAC.mdl
AD_DA/sysgenADCDAC_PreLoadFcn.m
AD_DA/test.fsdb
AD_DA/transcript
AD_DA/untitled.fda
AD_DA/xlcosim_dac_test_modelsim.tcl
AD_DA/xlcosim_dac_test_modelsim.vhd
AD_DA/xlcosim_dac_test_modelsimf.vhd
AD_DA/xlcosim_dac_test_modelsim_clk_drvr.vhd
AD_DA/work/_info
AD_DA/work/asr_ram/verilog.asm
AD_DA/work/asr_ram/_primary.dat
AD_DA/work/asr_ram/_primary.vhd
AD_DA/work/asr_ram
AD_DA/work/dac_test_black_box1_wrapper/verilog.asm
AD_DA/work/dac_test_black_box1_wrapper/_primary.dat
AD_DA/work/dac_test_black_box1_wrapper/_primary.vhd
AD_DA/work/dac_test_black_box1_wrapper
AD_DA/work/dac_test_black_box_wrapper/verilog.asm
AD_DA/work/dac_test_black_box_wrapper/_primary.dat
AD_DA/work/dac_test_black_box_wrapper/_primary.vhd
AD_DA/work/dac_test_black_box_wrapper
AD_DA/work/fir_160_tap/verilog.asm
AD_DA/work/fir_160_tap/_primary.dat
AD_DA/work/fir_160_tap/_primary.vhd
AD_DA/work/fir_160_tap
AD_DA/work/fir_asr/verilog.asm
AD_DA/work/fir_asr/_primary.dat
AD_DA/work/fir_asr/_primary.vhd
AD_DA/work/fir_asr
AD_DA/work/fir_mac/verilog.asm
AD_DA/work/fir_mac/_primary.dat
AD_DA/work/fir_mac/_primary.vhd
AD_DA/work/fir_mac
AD_DA/work/fir_rom/verilog.asm
AD_DA/work/fir_rom/_primary.dat
AD_DA/work/fir_rom/_primary.vhd
AD_DA/work/fir_rom
AD_DA/work/fir_top/verilog.asm
AD_DA/work/fir_top/_primary.dat
AD_DA/work/fir_top/_primary.vhd
AD_DA/work/fir_top
AD_DA/work/iir_6_filter/verilog.asm
AD_DA/work/iir_6_filter/_primary.dat
AD_DA/work/iir_6_filter/_primary.vhd
AD_DA/work/iir_6_filter
AD_DA/work/iir_filter/verilog.asm
AD_DA/work/iir_filter/_primary.dat
AD_DA/work/iir_filter/_primary.vhd
AD_DA/work/iir_filter
AD_DA/work/xlcosim_dac_test_modelsim/structural.asm
AD_DA/work/xlcosim_dac_test_modelsim/structural.dat
AD_DA/work/xlcosim_dac_test_modelsim/_primary.dat
AD_DA/work/xlcosim_dac_test_modelsim
AD_DA/work/xlcosim_dac_test_modelsim_clk_drvr/behavior.asm
AD_DA/work/xlcosim_dac_test_modelsim_clk_drvr/behavior.dat
AD_DA/work/xlcosim_dac_test_modelsim_clk_drvr/_primary.dat
AD_DA/work/xlcosim_dac_test_modelsim_clk_drvr
AD_DA/work/xlcosim_fli_controller/only.asm
AD_DA/work/xlcosim_fli_controller/only.dat
AD_DA/work/xlcosim_fli_controller/_primary.dat
AD_DA/work/xlcosim_fli_controller
AD_DA/work
AD_DA
www.dssz.com.txt
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