文件名称:adc_ctl
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AD采集芯片ADS8328的Verilog驱动代码，经过验证可用 -//Target IC: ADS8328(Read Frame Controlled via CS(FS=1)
// IC Descr iption: Manual Channel Select, CLK Period = 10MHz(1MHz-21MHz), CS_n Low to DataVaild [3ns,15ns]
// IC Time Sequence: da_tick = 50ns, da work period=da_tick*20=50*20=1000ns,
// Total Period=da_tick*25(conten a da_cs_n idle)
// Convst pin low for a minimum of 40 ns, Total Acquisition+ Conversion Cycle Time >=21CCLKs
// IC Descr iption: Manual Channel Select, CLK Period = 10MHz(1MHz-21MHz), CS_n Low to DataVaild [3ns,15ns]
// IC Time Sequence: da_tick = 50ns, da work period=da_tick*20=50*20=1000ns,
// Total Period=da_tick*25(conten a da_cs_n idle)
// Convst pin low for a minimum of 40 ns, Total Acquisition+ Conversion Cycle Time >=21CCLKs
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adc_ctl.v
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