文件名称:fenpin
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- 上传时间:2013-11-17
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文件大小:353.43kb
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介绍说明--下载内容来自于网络,使用问题请自行百度
这是一个二进制的最简单分频器,是一个简短的fpga代码,用verilog书写-This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
fenpin/
fenpin/db/
fenpin/db/FPQ.(0).cnf.cdb
fenpin/db/FPQ.(0).cnf.hdb
fenpin/db/FPQ.amm.cdb
fenpin/db/FPQ.asm.qmsg
fenpin/db/FPQ.asm.rdb
fenpin/db/FPQ.asm_labs.ddb
fenpin/db/FPQ.cbx.xml
fenpin/db/FPQ.cmp.bpm
fenpin/db/FPQ.cmp.cdb
fenpin/db/FPQ.cmp.hdb
fenpin/db/FPQ.cmp.kpt
fenpin/db/FPQ.cmp.logdb
fenpin/db/FPQ.cmp.rdb
fenpin/db/FPQ.cmp0.ddb
fenpin/db/FPQ.cmp1.ddb
fenpin/db/FPQ.cmp2.ddb
fenpin/db/FPQ.cmp_merge.kpt
fenpin/db/FPQ.db_info
fenpin/db/FPQ.eda.qmsg
fenpin/db/FPQ.fit.qmsg
fenpin/db/FPQ.hier_info
fenpin/db/FPQ.hif
fenpin/db/FPQ.idb.cdb
fenpin/db/FPQ.lpc.html
fenpin/db/FPQ.lpc.rdb
fenpin/db/FPQ.lpc.txt
fenpin/db/FPQ.map.bpm
fenpin/db/FPQ.map.cdb
fenpin/db/FPQ.map.hdb
fenpin/db/FPQ.map.kpt
fenpin/db/FPQ.map.logdb
fenpin/db/FPQ.map.qmsg
fenpin/db/FPQ.map_bb.cdb
fenpin/db/FPQ.map_bb.hdb
fenpin/db/FPQ.map_bb.logdb
fenpin/db/FPQ.pre_map.cdb
fenpin/db/FPQ.pre_map.hdb
fenpin/db/FPQ.rtlv.hdb
fenpin/db/FPQ.rtlv_sg.cdb
fenpin/db/FPQ.rtlv_sg_swap.cdb
fenpin/db/FPQ.sgdiff.cdb
fenpin/db/FPQ.sgdiff.hdb
fenpin/db/FPQ.sld_design_entry.sci
fenpin/db/FPQ.sld_design_entry_dsc.sci
fenpin/db/FPQ.smart_action.txt
fenpin/db/FPQ.sta.qmsg
fenpin/db/FPQ.sta.rdb
fenpin/db/FPQ.sta_cmp.8_slow.tdb
fenpin/db/FPQ.syn_hier_info
fenpin/db/FPQ.tis_db_list.ddb
fenpin/db/logic_util_heursitic.dat
fenpin/db/prev_cmp_FPQ.qmsg
fenpin/FPQ.asm.rpt
fenpin/FPQ.done
fenpin/FPQ.eda.rpt
fenpin/FPQ.fit.rpt
fenpin/FPQ.fit.smsg
fenpin/FPQ.fit.summary
fenpin/FPQ.flow.rpt
fenpin/FPQ.map.rpt
fenpin/FPQ.map.summary
fenpin/FPQ.pin
fenpin/FPQ.pof
fenpin/FPQ.qpf
fenpin/FPQ.qsf
fenpin/FPQ.sof
fenpin/FPQ.sta.rpt
fenpin/FPQ.sta.summary
fenpin/FPQ.v
fenpin/FPQ.v.bak
fenpin/FPQ_nativelink_simulation.rpt
fenpin/incremental_db/
fenpin/incremental_db/compiled_partitions/
fenpin/incremental_db/compiled_partitions/FPQ.db_info
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.cbp
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.cdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.dfp
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.hdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.kpt
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.logdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.rcfdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.re.rcfdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.map.cbp
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.map.cdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.map.dpi
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.map.hdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.map.kpt
fenpin/incremental_db/README
fenpin/simulation/
fenpin/simulation/modelsim/
fenpin/simulation/modelsim/FPQ.sft
fenpin/simulation/modelsim/FPQ.vo
fenpin/simulation/modelsim/FPQ_fast.vo
fenpin/simulation/modelsim/FPQ_modelsim.xrf
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak1
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak2
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak3
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak4
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak5
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak6
fenpin/simulation/modelsim/FPQ_v.sdo
fenpin/simulation/modelsim/FPQ_v_fast.sdo
fenpin/simulation/modelsim/modelsim.ini
fenpin/simulation/modelsim/msim_transcript
fenpin/simulation/modelsim/rtl_work/
fenpin/simulation/modelsim/rtl_work/@f@p@q/
fenpin/simulation/modelsim/rtl_work/@f@p@q/verilog.prw
fenpin/simulation/modelsim/rtl_work/@f@p@q/verilog.psm
fenpin/simulation/modelsim/rtl_work/@f@p@q/_primary.dat
fenpin/simulation/modelsim/rtl_work/@f@p@q/_primary.dbs
fenpin/simulation/modelsim/rtl_work/@f@p@q/_primary.vhd
fenpin/simulation/modelsim/rtl_work/time1/
fenpin/simulation/modelsim/rtl_work/time1/verilog.prw
fenpin/simulation/modelsim/rtl_work/time1/verilog.psm
fenpin/simulation/modelsim/rtl_work/time1/_primary.dat
fenpin/simulation/modelsim/rtl_work/time1/_primary.dbs
fenpin/simulation/modelsim/rtl_work/time1/_primary.vhd
fenpin/simulation/modelsim/rtl_work/_info
fenpin/simulation/modelsim/rtl_work/_temp/
fenpin/simulation/modelsim/rtl_work/_vmake
fenpin/simulation/modelsim/vsim.wlf
fenpin/time1.v
fenpin/time1.v.bak
fenpin/db/
fenpin/db/FPQ.(0).cnf.cdb
fenpin/db/FPQ.(0).cnf.hdb
fenpin/db/FPQ.amm.cdb
fenpin/db/FPQ.asm.qmsg
fenpin/db/FPQ.asm.rdb
fenpin/db/FPQ.asm_labs.ddb
fenpin/db/FPQ.cbx.xml
fenpin/db/FPQ.cmp.bpm
fenpin/db/FPQ.cmp.cdb
fenpin/db/FPQ.cmp.hdb
fenpin/db/FPQ.cmp.kpt
fenpin/db/FPQ.cmp.logdb
fenpin/db/FPQ.cmp.rdb
fenpin/db/FPQ.cmp0.ddb
fenpin/db/FPQ.cmp1.ddb
fenpin/db/FPQ.cmp2.ddb
fenpin/db/FPQ.cmp_merge.kpt
fenpin/db/FPQ.db_info
fenpin/db/FPQ.eda.qmsg
fenpin/db/FPQ.fit.qmsg
fenpin/db/FPQ.hier_info
fenpin/db/FPQ.hif
fenpin/db/FPQ.idb.cdb
fenpin/db/FPQ.lpc.html
fenpin/db/FPQ.lpc.rdb
fenpin/db/FPQ.lpc.txt
fenpin/db/FPQ.map.bpm
fenpin/db/FPQ.map.cdb
fenpin/db/FPQ.map.hdb
fenpin/db/FPQ.map.kpt
fenpin/db/FPQ.map.logdb
fenpin/db/FPQ.map.qmsg
fenpin/db/FPQ.map_bb.cdb
fenpin/db/FPQ.map_bb.hdb
fenpin/db/FPQ.map_bb.logdb
fenpin/db/FPQ.pre_map.cdb
fenpin/db/FPQ.pre_map.hdb
fenpin/db/FPQ.rtlv.hdb
fenpin/db/FPQ.rtlv_sg.cdb
fenpin/db/FPQ.rtlv_sg_swap.cdb
fenpin/db/FPQ.sgdiff.cdb
fenpin/db/FPQ.sgdiff.hdb
fenpin/db/FPQ.sld_design_entry.sci
fenpin/db/FPQ.sld_design_entry_dsc.sci
fenpin/db/FPQ.smart_action.txt
fenpin/db/FPQ.sta.qmsg
fenpin/db/FPQ.sta.rdb
fenpin/db/FPQ.sta_cmp.8_slow.tdb
fenpin/db/FPQ.syn_hier_info
fenpin/db/FPQ.tis_db_list.ddb
fenpin/db/logic_util_heursitic.dat
fenpin/db/prev_cmp_FPQ.qmsg
fenpin/FPQ.asm.rpt
fenpin/FPQ.done
fenpin/FPQ.eda.rpt
fenpin/FPQ.fit.rpt
fenpin/FPQ.fit.smsg
fenpin/FPQ.fit.summary
fenpin/FPQ.flow.rpt
fenpin/FPQ.map.rpt
fenpin/FPQ.map.summary
fenpin/FPQ.pin
fenpin/FPQ.pof
fenpin/FPQ.qpf
fenpin/FPQ.qsf
fenpin/FPQ.sof
fenpin/FPQ.sta.rpt
fenpin/FPQ.sta.summary
fenpin/FPQ.v
fenpin/FPQ.v.bak
fenpin/FPQ_nativelink_simulation.rpt
fenpin/incremental_db/
fenpin/incremental_db/compiled_partitions/
fenpin/incremental_db/compiled_partitions/FPQ.db_info
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.cbp
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.cdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.dfp
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.hdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.kpt
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.logdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.rcfdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.cmp.re.rcfdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.map.cbp
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.map.cdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.map.dpi
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.map.hdb
fenpin/incremental_db/compiled_partitions/FPQ.root_partition.map.kpt
fenpin/incremental_db/README
fenpin/simulation/
fenpin/simulation/modelsim/
fenpin/simulation/modelsim/FPQ.sft
fenpin/simulation/modelsim/FPQ.vo
fenpin/simulation/modelsim/FPQ_fast.vo
fenpin/simulation/modelsim/FPQ_modelsim.xrf
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak1
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak2
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak3
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak4
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak5
fenpin/simulation/modelsim/FPQ_run_msim_rtl_verilog.do.bak6
fenpin/simulation/modelsim/FPQ_v.sdo
fenpin/simulation/modelsim/FPQ_v_fast.sdo
fenpin/simulation/modelsim/modelsim.ini
fenpin/simulation/modelsim/msim_transcript
fenpin/simulation/modelsim/rtl_work/
fenpin/simulation/modelsim/rtl_work/@f@p@q/
fenpin/simulation/modelsim/rtl_work/@f@p@q/verilog.prw
fenpin/simulation/modelsim/rtl_work/@f@p@q/verilog.psm
fenpin/simulation/modelsim/rtl_work/@f@p@q/_primary.dat
fenpin/simulation/modelsim/rtl_work/@f@p@q/_primary.dbs
fenpin/simulation/modelsim/rtl_work/@f@p@q/_primary.vhd
fenpin/simulation/modelsim/rtl_work/time1/
fenpin/simulation/modelsim/rtl_work/time1/verilog.prw
fenpin/simulation/modelsim/rtl_work/time1/verilog.psm
fenpin/simulation/modelsim/rtl_work/time1/_primary.dat
fenpin/simulation/modelsim/rtl_work/time1/_primary.dbs
fenpin/simulation/modelsim/rtl_work/time1/_primary.vhd
fenpin/simulation/modelsim/rtl_work/_info
fenpin/simulation/modelsim/rtl_work/_temp/
fenpin/simulation/modelsim/rtl_work/_vmake
fenpin/simulation/modelsim/vsim.wlf
fenpin/time1.v
fenpin/time1.v.bak
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