基于FPGA的数字时钟设计，时钟可以按设定好的时间进行自动计时，FPGA板子上可以显示相应的时钟数字，是数字电路课程的一个课程设计，也是对于VHDL语言的一个熟悉过程.-FPGA-based digital clock design, the clock can be a good time to set automatic timing, FPGA board clock can display the corresponding figure is a digital circuit design courses, but also for the VHDL language, a familiar process.