lcd1602/dat与RS都是在EN的上升沿的时候读入数据！在下降沿的时候数据最稳定.bmp
lcd1602/db/lcd.(0).cnf.cdb
lcd1602/db/lcd.(0).cnf.hdb
lcd1602/db/lcd.amm.cdb
lcd1602/db/lcd.asm.qmsg
lcd1602/db/lcd.asm.rdb
lcd1602/db/lcd.cbx.xml
lcd1602/db/lcd.cmp.bpm
lcd1602/db/lcd.cmp.cdb
lcd1602/db/lcd.cmp.hdb
lcd1602/db/lcd.cmp.kpt
lcd1602/db/lcd.cmp.logdb
lcd1602/db/lcd.cmp.rdb
lcd1602/db/lcd.cmp0.ddb
lcd1602/db/lcd.cmp_merge.kpt
lcd1602/db/lcd.db_info
lcd1602/db/lcd.eda.qmsg
lcd1602/db/lcd.fit.qmsg
lcd1602/db/lcd.hier_info
lcd1602/db/lcd.hif
lcd1602/db/lcd.idb.cdb
lcd1602/db/lcd.lpc.html
lcd1602/db/lcd.lpc.rdb
lcd1602/db/lcd.lpc.txt
lcd1602/db/lcd.map.bpm
lcd1602/db/lcd.map.cdb
lcd1602/db/lcd.map.hdb
lcd1602/db/lcd.map.kpt
lcd1602/db/lcd.map.logdb
lcd1602/db/lcd.map.qmsg
lcd1602/db/lcd.map_bb.cdb
lcd1602/db/lcd.map_bb.hdb
lcd1602/db/lcd.map_bb.logdb
lcd1602/db/lcd.pre_map.cdb
lcd1602/db/lcd.pre_map.hdb
lcd1602/db/lcd.rtlv.hdb
lcd1602/db/lcd.rtlv_sg.cdb
lcd1602/db/lcd.rtlv_sg_swap.cdb
lcd1602/db/lcd.sgdiff.cdb
lcd1602/db/lcd.sgdiff.hdb
lcd1602/db/lcd.sld_design_entry.sci
lcd1602/db/lcd.sld_design_entry_dsc.sci
lcd1602/db/lcd.smart_action.txt
lcd1602/db/lcd.smp_dump.txt
lcd1602/db/lcd.sta.qmsg
lcd1602/db/lcd.sta.rdb
lcd1602/db/lcd.sta_cmp.8_slow.tdb
lcd1602/db/lcd.syn_hier_info
lcd1602/db/lcd.tis_db_list.ddb
lcd1602/db/lcd.tmw_info
lcd1602/db/logic_util_heursitic.dat
lcd1602/db/prev_cmp_lcd.qmsg
lcd1602/EN的时钟周期与扫描周期clkr相同.bmp
lcd1602/incremental_db/compiled_partitions/lcd.db_info
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.cmp.cdb
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.cmp.dfp
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.cmp.hdb
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.cmp.kpt
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.cmp.logdb
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.cmp.rcfdb
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.map.cdb
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.map.dpi
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.map.hbdb.cdb
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.map.hbdb.hb_info
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.map.hbdb.hdb
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.map.hbdb.sig
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.map.hdb
lcd1602/incremental_db/compiled_partitions/lcd.root_partition.map.kpt
lcd1602/incremental_db/README
lcd1602/lcd.asm.rpt
lcd1602/lcd.cdf
lcd1602/lcd.done
lcd1602/lcd.eda.rpt
lcd1602/lcd.fit.rpt
lcd1602/lcd.fit.smsg
lcd1602/lcd.fit.summary
lcd1602/lcd.flow.rpt
lcd1602/lcd.map.rpt
lcd1602/lcd.map.smsg
lcd1602/lcd.map.summary
lcd1602/lcd.pin
lcd1602/lcd.pof
lcd1602/lcd.qpf
lcd1602/lcd.qsf
lcd1602/lcd.sof
lcd1602/lcd.sta.rpt
lcd1602/lcd.sta.summary
lcd1602/lcd.v
lcd1602/lcd.v.bak
lcd1602/lcd_nativelink_simulation.rpt
lcd1602/simulation/modelsim/lcd.sft
lcd1602/simulation/modelsim/lcd.vo
lcd1602/simulation/modelsim/lcd.vt
lcd1602/simulation/modelsim/lcd.vt.bak
lcd1602/simulation/modelsim/lcd_modelsim.xrf
lcd1602/simulation/modelsim/lcd_run_msim_rtl_verilog.do
lcd1602/simulation/modelsim/lcd_run_msim_rtl_verilog.do.bak
lcd1602/simulation/modelsim/lcd_run_msim_rtl_verilog.do.bak1
lcd1602/simulation/modelsim/lcd_run_msim_rtl_verilog.do.bak2
lcd1602/simulation/modelsim/lcd_v.sdo
lcd1602/simulation/modelsim/modelsim.ini
lcd1602/simulation/modelsim/msim_transcript
lcd1602/simulation/modelsim/rtl_work/@_opt/vopt22b7ts
lcd1602/simulation/modelsim/rtl_work/@_opt/vopt2aw58y
lcd1602/simulation/modelsim/rtl_work/@_opt/vopt5zvwws
lcd1602/simulation/modelsim/rtl_work/@_opt/vopt6i04ts
lcd1602/simulation/modelsim/rtl_work/@_opt/vopt6th28y
lcd1602/simulation/modelsim/rtl_work/@_opt/vopt9fhsws
lcd1602/simulation/modelsim/rtl_work/@_opt/voptcz6nws
lcd1602/simulation/modelsim/rtl_work/@_opt/voptd1avts
lcd1602/simulation/modelsim/rtl_work/@_opt/voptgfwjws
lcd1602/simulation/modelsim/rtl_work/@_opt/voptghzrts
lcd1602/simulation/modelsim/rtl_work/@_opt/voptgsgm8y
lcd1602/simulation/modelsim/rtl_work/@_opt/voptk1mkts
lcd1602/simulation/modelsim/rtl_work/@_opt/voptk96i8y
lcd1602/simulation/modelsim/rtl_work/@_opt/voptqsvf8y
lcd1602/simulation/modelsim/rtl_work/@_opt/voptrhahts
lcd1602/simulation/modelsim/rtl_work/@_opt/voptv10ets
lcd1602/simulation/modelsim/rtl_work/@_opt/voptv9hb8y
lcd1602/simulation/modelsim/rtl_work/@_opt/voptys688y
lcd1602/simulation/modelsim/rtl_work/@_opt/voptzhmbts
lcd1602/simulation/modelsim/rtl_work/@_opt/_deps
lcd1602/simulation/modelsim/rtl_work/lcd/_primary.dat
lcd1602/simulation/modelsim/rtl_work/lcd/_primary.dbs
lcd1602/simulation/modelsim/rtl_work/lcd/_primary.vhd
lcd1602/simulation/modelsim/rtl_work/lcd_vlg_tst/_primary.dat
lcd1602/simulation/modelsim/rtl_work/lcd_vlg_tst/_primary.dbs
lcd1602/simulation/modelsim/rtl_work/lcd_vlg_tst/_primary.vhd
lcd1602/simulation/modelsim/rtl_work/_info
lcd1602/simulation/modelsim/rtl_work/_vmake
lcd1602/simulation/modelsim/tcl_stacktrace.txt
lcd1602/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_generic_pll_functions/_primary.da