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文件名称:minsoc

  • 所属分类：
    ARM-PowerPC-ColdFire-MIPS
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2013-12-11
  • 文件大小：
    9.83mb
  • 已下载：
    0次
  • 提 供 者：
    云***
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

片上处理器加上外设的设计,基于openrisc指令集，wishbone总线协议的一款基于FPGA的片上处理器-processor of on-chip
(系统自动生成,下载前可以参看下载内容)

下载文件列表

minsoc/branches/rc-1.0/backend/altera_3c25_board/altera_3c25_board.ucf
minsoc/branches/rc-1.0/backend/altera_3c25_board/board.h
minsoc/branches/rc-1.0/backend/altera_3c25_board/configure
minsoc/branches/rc-1.0/backend/altera_3c25_board/gcc-opt.mk
minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v
minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_defines.v
minsoc/branches/rc-1.0/backend/altera_3c25_board/orp.ld
minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/board.h
minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/configure
minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/gcc-opt.mk
minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v
minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_defines.v
minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/or1200_defines.v
minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/orp.ld
minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf
minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/board.h
minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/configure
minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/gcc-opt.mk
minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v
minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/minsoc_defines.v
minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/or1200_defines.v
minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/orp.ld
minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf
minsoc/branches/rc-1.0/backend/std/board.h
minsoc/branches/rc-1.0/backend/std/configure
minsoc/branches/rc-1.0/backend/std/gcc-opt.mk
minsoc/branches/rc-1.0/backend/std/minsoc_bench_defines.v
minsoc/branches/rc-1.0/backend/std/minsoc_defines.v
minsoc/branches/rc-1.0/backend/std/orp.ld
minsoc/branches/rc-1.0/backend/ug257/board.h
minsoc/branches/rc-1.0/backend/ug257/configure
minsoc/branches/rc-1.0/backend/ug257/gcc-opt.mk
minsoc/branches/rc-1.0/backend/ug257/minsoc_bench_defines.v
minsoc/branches/rc-1.0/backend/ug257/minsoc_defines.v
minsoc/branches/rc-1.0/backend/ug257/or1200_defines.v
minsoc/branches/rc-1.0/backend/ug257/orp.ld
minsoc/branches/rc-1.0/backend/ug257/ug257.ucf
minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v
minsoc/branches/rc-1.0/bench/verilog/minsoc_memory_model.v
minsoc/branches/rc-1.0/bench/verilog/sim_lib/fpga_memory_primitives.v
minsoc/branches/rc-1.0/bench/verilog/vpi/dbg_comm_vpi.v
minsoc/branches/rc-1.0/doc/lgpl-3.0.txt
minsoc/branches/rc-1.0/doc/minsoc.pdf
minsoc/branches/rc-1.0/doc/README.txt
minsoc/branches/rc-1.0/doc/src/minsoc.odt
minsoc/branches/rc-1.0/doc/src/figures/or1200.gif
minsoc/branches/rc-1.0/doc/src/figures/soc.odg
minsoc/branches/rc-1.0/prj/Makefile
minsoc/branches/rc-1.0/prj/scripts/altvhdprj.sh
minsoc/branches/rc-1.0/prj/scripts/altvprj.sh
minsoc/branches/rc-1.0/prj/scripts/simverilog.sh
minsoc/branches/rc-1.0/prj/scripts/simvhdl.sh
minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh
minsoc/branches/rc-1.0/prj/scripts/xilinxxst.sh
minsoc/branches/rc-1.0/prj/src/adbg_top.prj
minsoc/branches/rc-1.0/prj/src/altera_virtual_jtag.prj
minsoc/branches/rc-1.0/prj/src/ethmac.prj
minsoc/branches/rc-1.0/prj/src/jtag_top.prj
minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj
minsoc/branches/rc-1.0/prj/src/minsoc_top.prj
minsoc/branches/rc-1.0/prj/src/or1200_top.prj
minsoc/branches/rc-1.0/prj/src/uart_top.prj
minsoc/branches/rc-1.0/prj/src/blackboxes/adbg_top.v
minsoc/branches/rc-1.0/prj/src/blackboxes/ethmac.v
minsoc/branches/rc-1.0/prj/src/blackboxes/or1200_top.v
minsoc/branches/rc-1.0/prj/src/blackboxes/uart_top.v
minsoc/branches/rc-1.0/rtl/verilog/altera_pll.v
minsoc/branches/rc-1.0/rtl/verilog/minsoc_clock_manager.v
minsoc/branches/rc-1.0/rtl/verilog/minsoc_onchip_ram.v
minsoc/branches/rc-1.0/rtl/verilog/minsoc_onchip_ram_top.v
minsoc/branches/rc-1.0/rtl/verilog/minsoc_tc_top.v
minsoc/branches/rc-1.0/rtl/verilog/minsoc_top.v
minsoc/branches/rc-1.0/rtl/verilog/minsoc_xilinx_internal_jtag.v
minsoc/branches/rc-1.0/rtl/verilog/timescale.v
minsoc/branches/rc-1.0/rtl/verilog/xilinx_dcm.v
minsoc/branches/rc-1.0/rtl/verilog/minsoc_startup/OR1K_startup_generic.v
minsoc/branches/rc-1.0/rtl/verilog/minsoc_startup/spi_clgen.v
minsoc/branches/rc-1.0/rtl/verilog/minsoc_startup/spi_defines.v
minsoc/branches/rc-1.0/rtl/verilog/minsoc_startup/spi_shift.v
minsoc/branches/rc-1.0/rtl/verilog/minsoc_startup/spi_top.v
minsoc/branches/rc-1.0/rtl/verilog/or1200/bench/README
minsoc/branches/rc-1.0/rtl/verilog/or1200/doc/openrisc1200_spec.doc
minsoc/branches/rc-1.0/rtl/verilog/or1200/doc/openrisc1200_spec.pdf
minsoc/branches/rc-1.0/rtl/verilog/or1200/lib/README
minsoc/branches/rc-1.0/rtl/verilog/or1200/lint/bin/README
minsoc/branches/rc-1.0/rtl/verilog/or1200/lint/bin/run_lint
minsoc/branches/rc-1.0/rtl/verilog/or1200/lint/log/README
minsoc/branches/rc-1.0/rtl/verilog/or1200/lint/run/README
minsoc/branches/rc-1.0/rtl/verilog/or1200/rtl/verilog/or1200_alu.v
minsoc/branches/rc-1.0/rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
minsoc/branches/rc-1.0/rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
minsoc/branches/rc-1.0/rtl/verilog/or1200/rtl/verilog/or1200

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