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文件名称:16QAM

  • 所属分类：
    Other systems
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-12-27
  • 文件大小：
    503.21kb
  • 已下载：
    1次
  • 提 供 者：
    谢***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

QAM调制模块，可用于Quartus仿真与fpga硬件实现。-QAM Modulation Mode, can be used for Quartus simulation and FPGA.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

16QAM(verilog)/BPSKsend.asm.rpt
16QAM(verilog)/BPSKsend.bdf
16QAM(verilog)/BPSKsend.bsf
16QAM(verilog)/BPSKsend.cdf
16QAM(verilog)/BPSKsend.done
16QAM(verilog)/BPSKsend.dpf
16QAM(verilog)/BPSKsend.fit.rpt
16QAM(verilog)/BPSKsend.fit.smsg
16QAM(verilog)/BPSKsend.fit.summary
16QAM(verilog)/BPSKsend.flow.rpt
16QAM(verilog)/BPSKsend.map.rpt
16QAM(verilog)/BPSKsend.map.smsg
16QAM(verilog)/BPSKsend.map.summary
16QAM(verilog)/BPSKsend.pin
16QAM(verilog)/BPSKsend.qpf
16QAM(verilog)/BPSKsend.qsf
16QAM(verilog)/BPSKsend.qws
16QAM(verilog)/BPSKsend.sim.rpt
16QAM(verilog)/BPSKsend.sof
16QAM(verilog)/BPSKsend.sta.rpt
16QAM(verilog)/BPSKsend.sta.summary
16QAM(verilog)/BPSKsend.vwf
16QAM(verilog)/BPSKsend_assignment_defaults.qdf
16QAM(verilog)/DAC_out.bsf
16QAM(verilog)/DAC_out.v
16QAM(verilog)/DAC_out.v.bak
16QAM(verilog)/db/altsyncram_ag91.tdf
16QAM(verilog)/db/altsyncram_sc91.tdf
16QAM(verilog)/db/BPSKsend.analyze_file.qmsg
16QAM(verilog)/db/BPSKsend.db_info
16QAM(verilog)/db/BPSKsend.eco.cdb
16QAM(verilog)/db/BPSKsend.eda.qmsg
16QAM(verilog)/db/BPSKsend.sim.cvwf
16QAM(verilog)/db/BPSKsend.sld_design_entry.sci
16QAM(verilog)/db/BPSKsend_global_asgn_op.abo
16QAM(verilog)/db/PLL_280_altpll.v
16QAM(verilog)/db/prev_cmp_BPSKsend.asm.qmsg
16QAM(verilog)/db/prev_cmp_BPSKsend.fit.qmsg
16QAM(verilog)/db/prev_cmp_BPSKsend.map.qmsg
16QAM(verilog)/db/prev_cmp_BPSKsend.qmsg
16QAM(verilog)/db/prev_cmp_BPSKsend.sim.qmsg
16QAM(verilog)/db/prev_cmp_BPSKsend.sta.qmsg
16QAM(verilog)/db/wed.wsf
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.cmp.atm
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.cmp.cdb
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.cmp.dfp
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.cmp.hdb
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.cmp.hdbx
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.cmp.kpt
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.cmp.logdb
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.cmp.rcf
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.cmp.rcfdb
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.map.atm
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.map.cdb
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.map.dpi
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.map.hdb
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.map.hdbx
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.map.kpt
16QAM(verilog)/incremental_db/compiled_partitions/BPSKsend.root_partition.merge_hb.atm
16QAM(verilog)/incremental_db/README
16QAM(verilog)/NCO_BPSK.bsf
16QAM(verilog)/NCO_BPSK.v
16QAM(verilog)/NCO_BPSK.v.bak
16QAM(verilog)/output_file.map
16QAM(verilog)/output_file.pof
16QAM(verilog)/PLL_280.bsf
16QAM(verilog)/PLL_280.ppf
16QAM(verilog)/PLL_280.qip
16QAM(verilog)/PLL_280.v
16QAM(verilog)/PLL_280_bb.v
16QAM(verilog)/PLL_280_wave0.jpg
16QAM(verilog)/PLL_280_waveforms.html
16QAM(verilog)/ROM_COS.bsf
16QAM(verilog)/rom_cos.mif
16QAM(verilog)/ROM_COS.qip
16QAM(verilog)/ROM_COS.v
16QAM(verilog)/ROM_COS_bb.v
16QAM(verilog)/ROM_COS_wave0.jpg
16QAM(verilog)/ROM_COS_waveforms.html
16QAM(verilog)/ROM_NCOS.bsf
16QAM(verilog)/rom_ncos.mif
16QAM(verilog)/ROM_NCOS.qip
16QAM(verilog)/ROM_NCOS.v
16QAM(verilog)/ROM_NCOS_bb.v
16QAM(verilog)/ROM_NCOS_wave0.jpg
16QAM(verilog)/ROM_NCOS_waveforms.html
16QAM(verilog)/SpreadingCode.bsf
16QAM(verilog)/SpreadingCode.v
16QAM(verilog)/SpreadingCode.v.bak
16QAM(verilog)/incremental_db/compiled_partitions
16QAM(verilog)/db
16QAM(verilog)/incremental_db
16QAM(verilog)

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