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文件名称:CIC_4ORDER

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Matlab] [源码]
  • 上传时间：
    2014-01-03
  • 文件大小：
    3.46mb
  • 已下载：
    0次
  • 提 供 者：
    丛****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

4阶24倍抽取CIC滤波器的verilogHDL源代码，仿真测试代码及相关资料-4-order CIC decimation filter 24 times verilogHDL source code, simulation test code and related information
(系统自动生成,下载前可以参看下载内容)

下载文件列表

CIC_4ORDER/scr/cic_dec24.v
CIC_4ORDER/scr/cic_dec_arithmetic.v
CIC_4ORDER/scr/cic_filter_32add.v
CIC_4ORDER/scr/derivative_filter.v
CIC_4ORDER/scr/der_filter_27sub.v
CIC_4ORDER/scr/der_filter_dpram.v
CIC_4ORDER/scr/iqdata_24dec_adpram.v
CIC_4ORDER/scr/monopole_integrator_first.v
CIC_4ORDER/scr/multilevel_der_filter.v
CIC_4ORDER/scr/multilevel_integrator.v
CIC_4ORDER/scr/signal_gen0.v
CIC_4ORDER/scr/signal_gen1.v
CIC_4ORDER/scr/tb_cic.v
CIC_4ORDER/sim/fft_analyz_out.asv
CIC_4ORDER/sim/fft_analyz_out.m
CIC_4ORDER/sim/fft_analyz_signal.m
CIC_4ORDER/sim/out_data.dat
CIC_4ORDER/sim/signal_1m.dat
CIC_4ORDER/sim/signal_data.dat
CIC_4ORDER/sim/vsim.wlf
CIC_4ORDER/sim/wave.do
CIC_4ORDER/sim/wlftaeh4c2
CIC_4ORDER/sim/work/cic_dec24/verilog.asm
CIC_4ORDER/sim/work/cic_dec24/verilog.rw
CIC_4ORDER/sim/work/cic_dec24/_primary.dat
CIC_4ORDER/sim/work/cic_dec24/_primary.dbs
CIC_4ORDER/sim/work/cic_dec24/_primary.vhd
CIC_4ORDER/sim/work/cic_dec_arithmetic/verilog.asm
CIC_4ORDER/sim/work/cic_dec_arithmetic/verilog.rw
CIC_4ORDER/sim/work/cic_dec_arithmetic/_primary.dat
CIC_4ORDER/sim/work/cic_dec_arithmetic/_primary.dbs
CIC_4ORDER/sim/work/cic_dec_arithmetic/_primary.vhd
CIC_4ORDER/sim/work/derivative_filter/verilog.asm
CIC_4ORDER/sim/work/derivative_filter/verilog.rw
CIC_4ORDER/sim/work/derivative_filter/_primary.dat
CIC_4ORDER/sim/work/derivative_filter/_primary.dbs
CIC_4ORDER/sim/work/derivative_filter/_primary.vhd
CIC_4ORDER/sim/work/der_filter_27sub/verilog.asm
CIC_4ORDER/sim/work/der_filter_27sub/verilog.rw
CIC_4ORDER/sim/work/der_filter_27sub/_primary.dat
CIC_4ORDER/sim/work/der_filter_27sub/_primary.dbs
CIC_4ORDER/sim/work/der_filter_27sub/_primary.vhd
CIC_4ORDER/sim/work/monopole_integrator_first/verilog.asm
CIC_4ORDER/sim/work/monopole_integrator_first/verilog.rw
CIC_4ORDER/sim/work/monopole_integrator_first/_primary.dat
CIC_4ORDER/sim/work/monopole_integrator_first/_primary.dbs
CIC_4ORDER/sim/work/monopole_integrator_first/_primary.vhd
CIC_4ORDER/sim/work/multilevel_der_filter/verilog.asm
CIC_4ORDER/sim/work/multilevel_der_filter/verilog.rw
CIC_4ORDER/sim/work/multilevel_der_filter/_primary.dat
CIC_4ORDER/sim/work/multilevel_der_filter/_primary.dbs
CIC_4ORDER/sim/work/multilevel_der_filter/_primary.vhd
CIC_4ORDER/sim/work/multilevel_integrator/verilog.asm
CIC_4ORDER/sim/work/multilevel_integrator/verilog.rw
CIC_4ORDER/sim/work/multilevel_integrator/_primary.dat
CIC_4ORDER/sim/work/multilevel_integrator/_primary.dbs
CIC_4ORDER/sim/work/multilevel_integrator/_primary.vhd
CIC_4ORDER/sim/work/signal_gen0/verilog.asm
CIC_4ORDER/sim/work/signal_gen0/verilog.rw
CIC_4ORDER/sim/work/signal_gen0/_primary.dat
CIC_4ORDER/sim/work/signal_gen0/_primary.dbs
CIC_4ORDER/sim/work/signal_gen0/_primary.vhd
CIC_4ORDER/sim/work/signal_gen1/_primary.dat
CIC_4ORDER/sim/work/signal_gen1/_primary.dbs
CIC_4ORDER/sim/work/signal_gen1/_primary.vhd
CIC_4ORDER/sim/work/tb_cic/verilog.asm
CIC_4ORDER/sim/work/tb_cic/verilog.rw
CIC_4ORDER/sim/work/tb_cic/_primary.dat
CIC_4ORDER/sim/work/tb_cic/_primary.dbs
CIC_4ORDER/sim/work/tb_cic/_primary.vhd
CIC_4ORDER/sim/work/_info
CIC_4ORDER/sim/work/_temp/vlog31db4j
CIC_4ORDER/sim/work/_temp/vlog33f47y
CIC_4ORDER/sim/work/_temp/vlog398t9j
CIC_4ORDER/sim/work/_temp/vlog3g3517
CIC_4ORDER/sim/work/_temp/vlog3h8bkk
CIC_4ORDER/sim/work/_temp/vlog3im42w
CIC_4ORDER/sim/work/_temp/vlog4f1gnn
CIC_4ORDER/sim/work/_temp/vlogenee0y
CIC_4ORDER/sim/work/_temp/vlogf46nt9
CIC_4ORDER/sim/work/_temp/vlogf5gyrh
CIC_4ORDER/sim/work/_temp/vlogga6sq4
CIC_4ORDER/sim/work/_temp/vloggvfkxc
CIC_4ORDER/sim/work/_temp/vlogj32tts
CIC_4ORDER/sim/work/_temp/vlogtn4j4f
CIC_4ORDER/sim/work/_temp/vlogtw1sga
CIC_4ORDER/sim/work/_temp/vlogv74vyt
CIC_4ORDER/sim/work/_temp/vlogwct11x
CIC_4ORDER/sim/work/_temp/vlogz042h8
CIC_4ORDER/sim/work/_vmake
CIC_4ORDER/sim/work.mpf
CIC_4ORDER/sim_derivative_filter/data_generate.v
CIC_4ORDER/sim_derivative_filter/data_generate.v.bak
CIC_4ORDER/sim_derivative_filter/derivative_filter.v
CIC_4ORDER/sim_derivative_filter/derivative_filter.v.bak
CIC_4ORDER/sim_derivative_filter/derivative_filter_tb.v
CIC_4ORDER/sim_derivative_filter/derivative_filter_tb.v.bak
CIC_4ORDER/sim_derivative_filter/der_filter_27sub.v
CIC_4ORDER/sim_derivative_filter/vsim.wlf
CIC_4ORDER/sim_derivative_filter/work/data_generate/verilog.asm
CIC_4ORDER/sim_derivative_filter/work/data_generate/verilog.rw
CIC_4ORDER/sim_derivative_filter/work/data_generate/_primary.dat
CIC_4ORDER/sim_derivative_filter/work/data_generate/_primary.dbs
CIC_4ORDER/sim_derivative_filter/work/data_generate/_primary.vhd
CIC_4ORDER/sim_derivative_filter/work/derivative_filter/verilog.asm
CIC_4ORDER/sim_derivative_filter/work/derivative_filter/verilog.rw
CIC_4ORDER/sim_derivative_filter/work/derivative_filter/_primary.dat
CIC_4ORDER/sim_derivative_filter/work/derivative_filter/_primary.dbs
CIC_4ORDER/sim_derivative_filter/work/derivative_filter/_primary.vhd
CIC_4ORDER/sim_derivative_filter/work/derivative_filter_tb/verilog.asm
CIC_4ORDER/sim_derivative_filter/work/derivative_filter_tb/verilog.rw
CIC_4ORDER/sim_derivative_filter/work/derivative_filter_tb/_primary.dat
CIC_4ORDER/sim_der

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