文件名称:UART16450Transceiver-SourceCode.ZIP
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- 上传时间:2014-01-09
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文件大小:525kb
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串口16450的逻辑代码,内部带仿真测试代码,已经调试通过-Serial logic code 16450, with internal simulation test code has been debugging through
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下载文件列表
RD1169/
RD1169/constraints/
RD1169/doc/
RD1169/doc/RD1169.pdf
RD1169/doc/README_Simulation.txt
RD1169/doc/README_Synthesis.txt
RD1169/project/
RD1169/project/UART_16450_Transceiver/
RD1169/project/UART_16450_Transceiver/UART_16450_Transceiver_sbt.project
RD1169/project/UART_16450_Transceiver/UART_16450_Transceiver_syn.prj
RD1169/simulation/
RD1169/simulation/aldec/
RD1169/simulation/aldec/RD1169.do
RD1169/source/
RD1169/source/Verilog/
RD1169/source/Verilog/uart_16450_reg.v
RD1169/source/Verilog/uart_16450_transceiver.v
RD1169/source/Verilog/uart_master_controller.v
RD1169/source/Verilog/uart_rx_fsm.v
RD1169/source/Verilog/uart_transceiver.v
RD1169/source/Verilog/uart_tx_fsm.v
RD1169/testbench/
RD1169/testbench/Verilog/
RD1169/testbench/Verilog/globalvariables.v
RD1169/testbench/Verilog/loopback.v
RD1169/testbench/Verilog/readdatabuffer.v
RD1169/testbench/Verilog/readintridreg.v
RD1169/testbench/Verilog/readlinestatusreg.v
RD1169/testbench/Verilog/readmodemstatus.v
RD1169/testbench/Verilog/rxdatapathchk.v
RD1169/testbench/Verilog/sb_ice_lc.v
RD1169/testbench/Verilog/sb_ice_syn.v
RD1169/testbench/Verilog/setbaudrate.v
RD1169/testbench/Verilog/setdivisorlatch.v
RD1169/testbench/Verilog/setintrreg.v
RD1169/testbench/Verilog/setlinecntrlreg.v
RD1169/testbench/Verilog/setmodemcntrlreg.v
RD1169/testbench/Verilog/settxholdingreg.v
RD1169/testbench/Verilog/simulationdone.v
RD1169/testbench/Verilog/systasks.v
RD1169/testbench/Verilog/testcase.v
RD1169/testbench/Verilog/txdatapathchk.v
RD1169/testbench/Verilog/uart_16450_transceiver_tb.v
RD1169/testbench/Verilog/uart_16450_transceiver_wrapper.v
RD1169/testbench/Verilog/UART_16450_Transceiver_wrapper_synth.v
RD1169/constraints/
RD1169/doc/
RD1169/doc/RD1169.pdf
RD1169/doc/README_Simulation.txt
RD1169/doc/README_Synthesis.txt
RD1169/project/
RD1169/project/UART_16450_Transceiver/
RD1169/project/UART_16450_Transceiver/UART_16450_Transceiver_sbt.project
RD1169/project/UART_16450_Transceiver/UART_16450_Transceiver_syn.prj
RD1169/simulation/
RD1169/simulation/aldec/
RD1169/simulation/aldec/RD1169.do
RD1169/source/
RD1169/source/Verilog/
RD1169/source/Verilog/uart_16450_reg.v
RD1169/source/Verilog/uart_16450_transceiver.v
RD1169/source/Verilog/uart_master_controller.v
RD1169/source/Verilog/uart_rx_fsm.v
RD1169/source/Verilog/uart_transceiver.v
RD1169/source/Verilog/uart_tx_fsm.v
RD1169/testbench/
RD1169/testbench/Verilog/
RD1169/testbench/Verilog/globalvariables.v
RD1169/testbench/Verilog/loopback.v
RD1169/testbench/Verilog/readdatabuffer.v
RD1169/testbench/Verilog/readintridreg.v
RD1169/testbench/Verilog/readlinestatusreg.v
RD1169/testbench/Verilog/readmodemstatus.v
RD1169/testbench/Verilog/rxdatapathchk.v
RD1169/testbench/Verilog/sb_ice_lc.v
RD1169/testbench/Verilog/sb_ice_syn.v
RD1169/testbench/Verilog/setbaudrate.v
RD1169/testbench/Verilog/setdivisorlatch.v
RD1169/testbench/Verilog/setintrreg.v
RD1169/testbench/Verilog/setlinecntrlreg.v
RD1169/testbench/Verilog/setmodemcntrlreg.v
RD1169/testbench/Verilog/settxholdingreg.v
RD1169/testbench/Verilog/simulationdone.v
RD1169/testbench/Verilog/systasks.v
RD1169/testbench/Verilog/testcase.v
RD1169/testbench/Verilog/txdatapathchk.v
RD1169/testbench/Verilog/uart_16450_transceiver_tb.v
RD1169/testbench/Verilog/uart_16450_transceiver_wrapper.v
RD1169/testbench/Verilog/UART_16450_Transceiver_wrapper_synth.v
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