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文件名称:v2

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  • 上传时间:
    2014-01-14
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    3.83mb
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介绍说明--下载内容来自于网络,使用问题请自行百度

rs422串口指令控制以及AD7824芯片的数据采集-rs422 serial control timing
(系统自动生成,下载前可以参看下载内容)

下载文件列表

v2/
v2/V2.prj
v2/component/
v2/constraint/
v2/coreconsole/
v2/designer/
v2/designer/impl1/
v2/designer/impl1/AD_buffer.ide_des
v2/designer/impl1/AD_ctrl.ide_des
v2/designer/impl1/AD_gen.ide_des
v2/designer/impl1/GLXZ.ide_des
v2/designer/impl1/GLXZKZ.ide_des
v2/designer/impl1/GXLDQD.ide_des
v2/designer/impl1/GXLDQD.tcl
v2/designer/impl1/TOP-am.sdf
v2/designer/impl1/TOP.adb
v2/designer/impl1/TOP.adl
v2/designer/impl1/TOP.bit
v2/designer/impl1/TOP.dtf/
v2/designer/impl1/TOP.dtf/bitgen.log
v2/designer/impl1/TOP.dtf/floorplan-des.gcf
v2/designer/impl1/TOP.dtf/floorplan.gcf
v2/designer/impl1/TOP.dtf/floorplan.gcf.old
v2/designer/impl1/TOP.dtf/import.log
v2/designer/impl1/TOP.dtf/initial_placement.gcf
v2/designer/impl1/TOP.dtf/last_placement.gcf
v2/designer/impl1/TOP.dtf/masks
v2/designer/impl1/TOP.dtf/masks.final
v2/designer/impl1/TOP.dtf/master-des.gcf
v2/designer/impl1/TOP.dtf/master.gcf
v2/designer/impl1/TOP.dtf/mem_plmt.gcf
v2/designer/impl1/TOP.dtf/place.log
v2/designer/impl1/TOP.dtf/route.log
v2/designer/impl1/TOP.dtf/time.log
v2/designer/impl1/TOP.ide_des
v2/designer/impl1/TOP.stp
v2/designer/impl1/TOP.tcl
v2/designer/impl1/TOP_ba.sdf
v2/designer/impl1/TOP_ba.vhd
v2/designer/impl1/TOP_fp/
v2/designer/impl1/TOP_fp/TOP.log
v2/designer/impl1/TOP_fp/TOP.pro
v2/designer/impl1/TOP_fp/projectData/
v2/designer/impl1/TOP_fp/projectData/TOP.stp
v2/designer/impl1/TPSP.ide_des
v2/designer/impl1/ZFGB.ide_des
v2/designer/impl1/ZFKG.ide_des
v2/designer/impl1/clk_gen.ide_des
v2/designer/impl1/cmd_io.ide_des
v2/designer/impl1/cmd_rec.ide_des
v2/designer/impl1/designer.log
v2/designer/impl1/designer_synth_check.log
v2/designer/impl1/fre_sel.ide_des
v2/designer/impl1/global_reset.ide_des
v2/designer/impl1/pll80.ide_des
v2/designer/impl1/pll80.tcl
v2/designer/impl1/project/
v2/designer/impl1/project/project.log
v2/designer/impl1/project/project.pro
v2/designer/impl1/rx.ide_des
v2/designer/impl1/simulation/
v2/designer/impl1/tx.ide_des
v2/designer/impl1/updata.ide_des
v2/hdl/
v2/hdl/AD_ctrl.vhd
v2/hdl/AD_gen.vhd
v2/hdl/GLXZ.vhd
v2/hdl/GLXZKL.vhd
v2/hdl/GLXZKL.vhd.lnk
v2/hdl/GXLDQD.vhd
v2/hdl/TOP.vhd
v2/hdl/TOP.vhd.lnk
v2/hdl/TPSP.vhd
v2/hdl/ZFKG.vhd
v2/hdl/__Previews/
v2/hdl/__Previews/TOP.vhdPreview
v2/hdl/clk_gen.vhd
v2/hdl/cmd_io.vhd
v2/hdl/cmd_rec.vhd
v2/hdl/fre_sel.vhd
v2/hdl/global_reset.vhd
v2/hdl/rx.vhd
v2/hdl/tx.vhd
v2/hdl/updata.vhd
v2/hdl/waveperl.log
v2/phy_synthesis/
v2/simulation/
v2/simulation/modelsim.ini
v2/simulation/modelsim.ini.sav
v2/simulation/modelsim.log
v2/simulation/postsynth/
v2/simulation/postsynth/_info
v2/simulation/postsynth/_temp/
v2/simulation/postsynth/_vmake
v2/simulation/postsynth/gxldqd/
v2/simulation/postsynth/gxldqd/_primary.dat
v2/simulation/postsynth/gxldqd/_primary.dbs
v2/simulation/postsynth/gxldqd/def_arch.dat
v2/simulation/postsynth/gxldqd/def_arch.dbs
v2/simulation/postsynth/gxldqd/def_arch.psm
v2/simulation/postsynth/pll80/
v2/simulation/postsynth/pll80/_primary.dat
v2/simulation/postsynth/pll80/_primary.dbs
v2/simulation/postsynth/pll80/def_arch.dat
v2/simulation/postsynth/pll80/def_arch.dbs
v2/simulation/postsynth/pll80/def_arch.psm
v2/simulation/postsynth/stimulus/
v2/simulation/postsynth/stimulus/_primary.dat
v2/simulation/postsynth/stimulus/_primary.dbs
v2/simulation/postsynth/stimulus/stimulator.dat
v2/simulation/postsynth/stimulus/stimulator.dbs
v2/simulation/postsynth/stimulus/stimulator.psm
v2/simulation/postsynth/testbench/
v2/simulation/postsynth/testbench/_primary.dat
v2/simulation/postsynth/testbench/_primary.dbs
v2/simulation/postsynth/testbench/tbgeneratedcode.dat
v2/simulation/postsynth/testbench/tbgeneratedcode.dbs
v2/simulation/postsynth/testbench/tbgeneratedcode.psm
v2/simulation/presynth/
v2/simulation/presynth/_info
v2/simulation/presynth/_temp/
v2/simulation/presynth/_vmake
v2/simulation/presynth/clk_gen/
v2/simulation/presynth/clk_gen/_primary.dat
v2/simulation/presynth/clk_gen/_primary.dbs
v2/simulation/presynth/clk_gen/behavioral.dat
v2/simulation/presynth/clk_gen/behavioral.dbs
v2/simulation/presynth/clk_gen/behavioral.psm
v2/simulation/presynth/gxldqd/
v2/simulation/presynth/gxldqd/_primary.dat
v2/simulation/presynth/gxldqd/_primary.dbs
v2/simulation/presynth/gxldqd/behavioral.dat
v2/simulation/presynth/gxldqd/behavioral.dbs
v2/simulation/presynth/gxldqd/behavioral.psm
v2/simulation/presynth/stimulus/
v2/simulation/presynth/stimulus/_primary.dat
v2/simulation/presynth/stimulus/_primary.dbs
v2/simulation/presynth/stimulus/stimulator.dat
v2/simulation/presynth/stimulus/stimulator.dbs
v2/simulation/presynth/stimulus/stimulator.psm
v2/simulation/presynth/testbench/
v2/simulation/presynth/testbench/_primary.dat
v2/simulation/presynth/testbench/_primary.dbs
v2/simulation/presynth/testbench/tbgeneratedcode.dat
v2/simulation/presynth/testbench/tbgeneratedcode.dbs
v2/simulation/presynth/testbench/tbgeneratedcode.psm
v2/simulation/run.do
v2/simulation/tb.log
v2/simulation/vsim.wlf
v2/smartgen/
v2/smartgen/AD_buffer/
v2/smartgen/AD_buffer/AD_buffer.cxf
v2/smartgen/AD_buffer/AD_buffer.gen
v2/smartgen/AD_buffer/AD_buffer.log
v2/smartgen/AD_buffer/AD_buffer.vhd
v2/smartgen/AD_buffer/AD

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