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文件名称:11061101469955

  • 所属分类：
    Driver develop
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2014-01-16
  • 文件大小：
    1.39mb
  • 已下载：
    0次
  • 提 供 者：
    l***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

This a 8051CPU core with Jtag, inclue all source code by verilog.-This is a 8051CPU core with Jtag, inclue all source code by verilog.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

WISHBONE Interconnect Matrix IP CORE/wb_conmax/bench/verilog/tests.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/bench/verilog/test_bench_top.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/bench/verilog/wb_mast_model.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/bench/verilog/wb_model_defines.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/bench/verilog/wb_slv_model.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/doc/conmax.pdf
WISHBONE Interconnect Matrix IP CORE/wb_conmax/doc/README.txt
WISHBONE Interconnect Matrix IP CORE/wb_conmax/doc/STATUS.txt
WISHBONE Interconnect Matrix IP CORE/wb_conmax/rtl/verilog/wb_conmax_arb.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/rtl/verilog/wb_conmax_defines.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/rtl/verilog/wb_conmax_master_if.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/rtl/verilog/wb_conmax_msel.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/rtl/verilog/wb_conmax_rf.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/rtl/verilog/wb_conmax_top.v
WISHBONE Interconnect Matrix IP CORE/wb_conmax/sim/rtl_sim/bin/Makefile
WISHBONE Interconnect Matrix IP CORE/wb_conmax/sim/rtl_sim/run/ncwork/CVS/Entries
WISHBONE Interconnect Matrix IP CORE/wb_conmax/sim/rtl_sim/run/ncwork/CVS/Repository
WISHBONE Interconnect Matrix IP CORE/wb_conmax/sim/rtl_sim/run/ncwork/CVS/Root
WISHBONE Interconnect Matrix IP CORE/wb_conmax/sim/rtl_sim/run/waves/CVS/Entries
WISHBONE Interconnect Matrix IP CORE/wb_conmax/sim/rtl_sim/run/waves/CVS/Repository
WISHBONE Interconnect Matrix IP CORE/wb_conmax/sim/rtl_sim/run/waves/CVS/Root
WISHBONE Interconnect Matrix IP CORE/wb_conmax/sim/rtl_sim/run/waves/waves.do
WISHBONE Interconnect Matrix IP CORE/wb_conmax/syn/bin/.read.dc.swp
WISHBONE Interconnect Matrix IP CORE/wb_conmax/syn/bin/comp.dc
WISHBONE Interconnect Matrix IP CORE/wb_conmax/syn/bin/design_spec.dc
WISHBONE Interconnect Matrix IP CORE/wb_conmax/syn/bin/lib_spec.dc
WISHBONE Interconnect Matrix IP CORE/wb_conmax/syn/bin/read.dc
8051/8051core-Verilog/8051core-Verilog/Acc.v
8051/8051core-Verilog/8051core-Verilog/All.v
8051/8051core-Verilog/8051core-Verilog/Alu.v
8051/8051core-Verilog/8051core-Verilog/alu_src1_sel.v
8051/8051core-Verilog/8051core-Verilog/alu_src2_sel.v
8051/8051core-Verilog/8051core-Verilog/alu_src3_sel.v
8051/8051core-Verilog/8051core-Verilog/Comp.v
8051/8051core-Verilog/8051core-Verilog/cy_select.v
8051/8051core-Verilog/8051core-Verilog/Decoder.v
8051/8051core-Verilog/8051core-Verilog/Defines.v
8051/8051core-Verilog/8051core-Verilog/Divide.v
8051/8051core-Verilog/8051core-Verilog/Dptr.v
8051/8051core-Verilog/8051core-Verilog/ext_addr_sel.v
8051/8051core-Verilog/8051core-Verilog/immediate_sel.v
8051/8051core-Verilog/8051core-Verilog/IndiAddr.v
8051/8051core-Verilog/8051core-Verilog/Make
8051/8051core-Verilog/8051core-Verilog/Multiply.v
8051/8051core-Verilog/8051core-Verilog/op_select.v
8051/8051core-Verilog/8051core-Verilog/Pc.v
8051/8051core-Verilog/8051core-Verilog/Port_out.v
8051/8051core-Verilog/8051core-Verilog/Psw.v
8051/8051core-Verilog/8051core-Verilog/Ram.v
8051/8051core-Verilog/8051core-Verilog/ram_rd_sel.v
8051/8051core-Verilog/8051core-Verilog/Ram_sel.v
8051/8051core-Verilog/8051core-Verilog/ram_wr_sel.v
8051/8051core-Verilog/8051core-Verilog/Reg1.v
8051/8051core-Verilog/8051core-Verilog/Reg2.v
8051/8051core-Verilog/8051core-Verilog/Reg3.v
8051/8051core-Verilog/8051core-Verilog/Reg4.v
8051/8051core-Verilog/8051core-Verilog/Reg5.v
8051/8051core-Verilog/8051core-Verilog/Reg8.v
8051/8051core-Verilog/8051core-Verilog/Reg8r.v
8051/8051core-Verilog/8051core-Verilog/Rom.v
8051/8051core-Verilog/8051core-Verilog/rom_addr_sel.v
8051/8051core-Verilog/8051core-Verilog/Sp.v
8051/8051core-Verilog/8051core-Verilog/Tb_all.v
8051/8051core-Verilog/8051core-Verilog/transcript
cpu/alu.v
cpu/alucell.v
cpu/alumux.v
cpu/control.v
cpu/control_wopc.v
cpu/counter.v
cpu/cpu.v
cpu/galu.v
cpu/mem.v
cpu/shr.v
i2c/bench/verilog/CVS/Entries
i2c/bench/verilog/CVS/Repository
i2c/bench/verilog/CVS/Root
i2c/bench/verilog/i2c_slave_model.v
i2c/bench/verilog/spi_slave_model.v
i2c/bench/verilog/tst_bench_top.v
i2c/bench/verilog/wb_master_model.v
i2c/doc/i2c_specs.pdf
i2c/doc/src/I2C_specs.doc
i2c/rtl/verilog/i2c_master_bit_ctrl.v
i2c/rtl/verilog/i2c_master_byte_ctrl.v
i2c/rtl/verilog/i2c_master_defines.v
i2c/rtl/verilog/i2c_master_top.v
i2c/rtl/verilog/timescale.v
i2c/rtl/vhdl/I2C.VHD
i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
i2c/rtl/vhdl/i2c_master_top.vhd
i2c/rtl/vhdl/readme
i2c/rtl/vhdl/tst_ds1621.vhd
i2c/software/include/oc_i2c_master.h
jtag/tap/doc/jtag.pdf
jtag/tap/doc/src/jtag.doc
jtag/tap/rtl/verilog/tap_defines.v
jtag/tap/rtl/verilog/tap_top.v
vgalcd/vga_lcd/bench/verilog/sync_check.v
vgalcd/vga_lcd/bench/verilog/tests.v
vgalcd/vga_lcd/bench/verilog/test_bench_top.v
vgalcd/vga_lcd/bench/verilog/wb_b3_check.v
vgalcd/vga_lcd/bench

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