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文件名称:synchoronous_FIFO(jianban)

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2014-01-23
  • 文件大小：
    662.48kb
  • 已下载：
    0次
  • 提 供 者：
    杨***
  • 相关连接：
    无
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基于IPcore的同步FIFO的设计。采用Verilog代码书写。读写位宽均为8bit，深度为32.-IPcore synchronous FIFO-based design. Using Verilog code writing. Read and write bits wide are 8bit, depth is 32.
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下载文件列表

synchoronous_FIFO(jianban)/
synchoronous_FIFO(jianban)/fuse.log
synchoronous_FIFO(jianban)/fuse.xmsgs
synchoronous_FIFO(jianban)/fuseRelaunch.cmd
synchoronous_FIFO(jianban)/ipcore_dir/
synchoronous_FIFO(jianban)/ipcore_dir/coregen.cgp
synchoronous_FIFO(jianban)/ipcore_dir/coregen.log
synchoronous_FIFO(jianban)/ipcore_dir/create_RAM.tcl
synchoronous_FIFO(jianban)/ipcore_dir/edit_RAM.tcl
synchoronous_FIFO(jianban)/ipcore_dir/RAM/
synchoronous_FIFO(jianban)/ipcore_dir/RAM.asy
synchoronous_FIFO(jianban)/ipcore_dir/RAM.gise
synchoronous_FIFO(jianban)/ipcore_dir/RAM.ncf
synchoronous_FIFO(jianban)/ipcore_dir/RAM.ngc
synchoronous_FIFO(jianban)/ipcore_dir/RAM.sym
synchoronous_FIFO(jianban)/ipcore_dir/RAM.v
synchoronous_FIFO(jianban)/ipcore_dir/RAM.veo
synchoronous_FIFO(jianban)/ipcore_dir/RAM.xco
synchoronous_FIFO(jianban)/ipcore_dir/RAM.xise
synchoronous_FIFO(jianban)/ipcore_dir/RAM/blk_mem_gen_v7_3_readme.txt
synchoronous_FIFO(jianban)/ipcore_dir/RAM/doc/
synchoronous_FIFO(jianban)/ipcore_dir/RAM/doc/blk_mem_gen_v7_3_vinfo.html
synchoronous_FIFO(jianban)/ipcore_dir/RAM/doc/pg058-blk-mem-gen.pdf
synchoronous_FIFO(jianban)/ipcore_dir/RAM/example_design/
synchoronous_FIFO(jianban)/ipcore_dir/RAM/example_design/RAM_exdes.ucf
synchoronous_FIFO(jianban)/ipcore_dir/RAM/example_design/RAM_exdes.vhd
synchoronous_FIFO(jianban)/ipcore_dir/RAM/example_design/RAM_exdes.xdc
synchoronous_FIFO(jianban)/ipcore_dir/RAM/example_design/RAM_prod.vhd
synchoronous_FIFO(jianban)/ipcore_dir/RAM/implement/
synchoronous_FIFO(jianban)/ipcore_dir/RAM/implement/implement.bat
synchoronous_FIFO(jianban)/ipcore_dir/RAM/implement/implement.sh
synchoronous_FIFO(jianban)/ipcore_dir/RAM/implement/planAhead_ise.bat
synchoronous_FIFO(jianban)/ipcore_dir/RAM/implement/planAhead_ise.sh
synchoronous_FIFO(jianban)/ipcore_dir/RAM/implement/planAhead_ise.tcl
synchoronous_FIFO(jianban)/ipcore_dir/RAM/implement/xst.prj
synchoronous_FIFO(jianban)/ipcore_dir/RAM/implement/xst.scr
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/addr_gen.vhd
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/bmg_stim_gen.vhd
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/bmg_tb_pkg.vhd
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/checker.vhd
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/data_gen.vhd
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/functional/
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/functional/simcmds.tcl
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/functional/simulate_isim.bat
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/functional/simulate_mti.bat
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/functional/simulate_mti.do
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/functional/simulate_mti.sh
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/functional/simulate_ncsim.sh
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/functional/simulate_vcs.sh
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/functional/ucli_commands.key
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/functional/vcs_session.tcl
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/functional/wave_mti.do
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/functional/wave_ncsim.sv
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/RAM_synth.vhd
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/RAM_tb.vhd
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/random.vhd
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/timing/
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/timing/simcmds.tcl
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/timing/simulate_isim.bat
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/timing/simulate_mti.bat
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/timing/simulate_mti.do
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/timing/simulate_mti.sh
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/timing/simulate_ncsim.sh
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/timing/simulate_vcs.sh
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/timing/ucli_commands.key
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/timing/vcs_session.tcl
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/timing/wave_mti.do
synchoronous_FIFO(jianban)/ipcore_dir/RAM/simulation/timing/wave_ncsim.sv
synchoronous_FIFO(jianban)/ipcore_dir/RAM_flist.txt
synchoronous_FIFO(jianban)/ipcore_dir/RAM_xmdf.tcl
synchoronous_FIFO(jianban)/ipcore_dir/summary.log
synchoronous_FIFO(jianban)/ipcore_dir/tmp/
synchoronous_FIFO(jianban)/ipcore_dir/tmp/RAM.lso
synchoronous_FIFO(jianban)/ipcore_dir/tmp/_cg/
synchoronous_FIFO(jianban)/ipcore_dir/tmp/_xmsgs/
synchoronous_FIFO(jianban)/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
synchoronous_FIFO(jianban)/ipcore_dir/tmp/_xmsgs/xst.xmsgs
synchoronous_FIFO(jianban)/ipcore_dir/xlnx_auto_0_xdb/
synchoronous_FIFO(jianban)/ipcore_dir/_xmsgs/
synchoronous_FIFO(jianban)/ipcore_dir/_xmsgs/cg.xmsgs
synchoronous_FIFO(jianban)/ipcore_dir/_xmsgs/pn_parser.xmsgs
synchoronous_FIFO(jianban)/iseconfig/
synchoronous_FIFO(ji

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