文件名称:sine
介绍说明--下载内容来自于网络,使用问题请自行百度
用verilog语言编的正弦波发生器,可以用QuartusII来打开这个源码,也可以转换成VHDL语言
(系统自动生成,下载前可以参看下载内容)
下载文件列表
sine/default.cfg
sine/default.cfg.bck
sine/ROM.DAT
sine/rom16x7.v
sine/sgen.c
sine/sim.vc
sine/simv.exe
sine/simv.exp
sine/simv.lib
sine/sine.v
sine/sinetest.v
sine/vcdplus.vpd
sine/wave.bat
sine/simv.daidir/01j9_1.daidb
sine/simv.daidir/3e3i_1.daidb
sine/simv.daidir/vcs.dailu
sine/simv.daidir/vcs_mstr.daidb
sine/simv.daidir
sine
sine/default.cfg.bck
sine/ROM.DAT
sine/rom16x7.v
sine/sgen.c
sine/sim.vc
sine/simv.exe
sine/simv.exp
sine/simv.lib
sine/sine.v
sine/sinetest.v
sine/vcdplus.vpd
sine/wave.bat
sine/simv.daidir/01j9_1.daidb
sine/simv.daidir/3e3i_1.daidb
sine/simv.daidir/vcs.dailu
sine/simv.daidir/vcs_mstr.daidb
sine/simv.daidir
sine
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