文件名称:verilog_study
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it about using veriolog complement some project,thanks!
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下载文件列表
verilog_study/first.v
verilog_study/Desktop_.ini
verilog_study/compare.v
verilog_study/compare_test.v
verilog_study/half_clk.v
verilog_study/half_clk_test.v
verilog_study/division.v
verilog_study/BLOCKING.V
verilog_study/division--.v
verilog_study/alu(use always).v
verilog_study/function.v
verilog_study/task.v
verilog_study/FSM.V
verilog_study/writing.v
verilog_study/emob_module.v
verilog_study/1.v
verilog_study/test.v
verilog_study/compare_test.v.bak
verilog_study
verilog_study/Desktop_.ini
verilog_study/compare.v
verilog_study/compare_test.v
verilog_study/half_clk.v
verilog_study/half_clk_test.v
verilog_study/division.v
verilog_study/BLOCKING.V
verilog_study/division--.v
verilog_study/alu(use always).v
verilog_study/function.v
verilog_study/task.v
verilog_study/FSM.V
verilog_study/writing.v
verilog_study/emob_module.v
verilog_study/1.v
verilog_study/test.v
verilog_study/compare_test.v.bak
verilog_study
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