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文件名称:lutsr

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  • 上传时间:
    2014-02-19
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    661.08kb
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verilog design of lut sr random number generator
(系统自动生成,下载前可以参看下载内容)

下载文件列表

lutsr/.lso
lutsr/code.vhd
lutsr/code_summary.html
lutsr/isim/work/hdllib.ref
lutsr/isim/work/hdpdeps.ref
lutsr/isim/work/rng_n1024_r32_t5_k32_s1c48/mingw/rtl.obj
lutsr/isim/work/rng_n1024_r32_t5_k32_s1c48/rtl.h
lutsr/isim/work/rng_n1024_r32_t5_k32_s1c48_sr/mingw/rtl.obj
lutsr/isim/work/rng_n1024_r32_t5_k32_s1c48_sr/rtl.h
lutsr/isim/work/sub00/vhpl00.vho
lutsr/isim/work/sub00/vhpl01.vho
lutsr/isim/work/sub00/vhpl02.vho
lutsr/isim/work/sub00/vhpl03.vho
lutsr/isim/work/sub00/vhpl04.vho
lutsr/isim/work/sub00/vhpl05.vho
lutsr/isim/work/sub00/vhpl06.vho
lutsr/isim/work/sub00/vhpl07.vho
lutsr/isim/work/test/mingw/testbench_arch.obj
lutsr/isim/work/test/testbench_arch.h
lutsr/isim/work/test/xsimtestbench_arch.cpp
lutsr/isim/work/test_rng_n1024_r32_t5_k32_s1c48/behavior.h
lutsr/isim/work/test_rng_n1024_r32_t5_k32_s1c48/mingw/behavior.obj
lutsr/isim/work/test_rng_n1024_r32_t5_k32_s1c48/xsimbehavior.cpp
lutsr/isim.cmd
lutsr/isim.hdlsourcefiles
lutsr/isim.log
lutsr/isim.tmp_save/_1
lutsr/isimwavedata.xwv
lutsr/jhyu.vhd
lutsr/lutsr.ise
lutsr/lutsr.ise_ISE_Backup
lutsr/lutsr.ntrc_log
lutsr/pepExtractor.prj
lutsr/results.txt
lutsr/rng_n1024_r32_t5_k32_s1c48.cmd_log
lutsr/rng_n1024_r32_t5_k32_s1c48.lso
lutsr/rng_n1024_r32_t5_k32_s1c48.ngc
lutsr/rng_n1024_r32_t5_k32_s1c48.ngr
lutsr/rng_n1024_r32_t5_k32_s1c48.prj
lutsr/rng_n1024_r32_t5_k32_s1c48.stx
lutsr/rng_n1024_r32_t5_k32_s1c48.syr
lutsr/rng_n1024_r32_t5_k32_s1c48.xst
lutsr/rng_n1024_r32_t5_k32_s1c48_SR.prj
lutsr/rng_n1024_r32_t5_k32_s1c48_SR.stx
lutsr/rng_n1024_r32_t5_k32_s1c48_SR.xst
lutsr/rng_n1024_r32_t5_k32_s1c48_SR_vhdl.prj
lutsr/rng_n1024_r32_t5_k32_s1c48_summary.html
lutsr/rng_n1024_r32_t5_k32_s1c48_vhdl.prj
lutsr/test.ant
lutsr/test.jhd
lutsr/test.tbw
lutsr/test.vhw
lutsr/test.xwv
lutsr/test.xwv_bak
lutsr/test1.xwv
lutsr/test1.xwv_bak
lutsr/test12.xwv
lutsr/test12.xwv_bak
lutsr/test12_bencher.prj
lutsr/test1_bencher.prj
lutsr/test_beh.prj
lutsr/test_bencher.prj
lutsr/test_isim_beh.exe
lutsr/test_rng_n1024_r32_t5_k32_s1c48_beh.prj
lutsr/test_rng_n1024_r32_t5_k32_s1c48_isim_beh.exe
lutsr/xilinxsim.ini
lutsr/xst/dump.xst/rng_n1024_r32_t5_k32_s1c48.prj/ntrc.scr
lutsr/xst/work/hdllib.ref
lutsr/xst/work/hdpdeps.ref
lutsr/xst/work/sub00/vhpl00.vho
lutsr/xst/work/sub00/vhpl01.vho
lutsr/xst/work/sub00/vhpl02.vho
lutsr/xst/work/sub00/vhpl03.vho
lutsr/_xmsgs/fuse.xmsgs
lutsr/_xmsgs/vhpcomp.xmsgs
lutsr/_xmsgs/xst.xmsgs
lutsr/xst/dump.xst/rng_n1024_r32_t5_k32_s1c48.prj/ngx/notopt
lutsr/xst/dump.xst/rng_n1024_r32_t5_k32_s1c48.prj/ngx/opt
lutsr/isim/work/rng_n1024_r32_t5_k32_s1c48/mingw
lutsr/isim/work/rng_n1024_r32_t5_k32_s1c48_sr/mingw
lutsr/isim/work/test/mingw
lutsr/isim/work/test_rng_n1024_r32_t5_k32_s1c48/mingw
lutsr/xst/dump.xst/rng_n1024_r32_t5_k32_s1c48.prj/ngx
lutsr/isim/work/rng_n1024_r32_t5_k32_s1c48
lutsr/isim/work/rng_n1024_r32_t5_k32_s1c48_sr
lutsr/isim/work/sub00
lutsr/isim/work/test
lutsr/isim/work/test_rng_n1024_r32_t5_k32_s1c48
lutsr/xst/dump.xst/rng_n1024_r32_t5_k32_s1c48.prj
lutsr/xst/work/sub00
lutsr/isim/file graph
lutsr/isim/work
lutsr/xst/dump.xst
lutsr/xst/projnav.tmp
lutsr/xst/work
lutsr/isim
lutsr/isim.tmp_save
lutsr/xst
lutsr/_xmsgs
lutsr

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