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文件名称:CPLDLCD1602

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2014-02-28
  • 文件大小：
    3.38mb
  • 已下载：
    0次
  • 提 供 者：
    裴***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

CPLD控制液晶字符屏LCD1602显示-CPLD CONTROL LCD1602
(系统自动生成,下载前可以参看下载内容)

下载文件列表

CPLDLCD1602/
CPLDLCD1602/an497.pdf
CPLDLCD1602/an497_CN.pdf
CPLDLCD1602/an497_design_example.zip
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/code/
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/code/lcd_controller.v
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/lcd_controller.cr.mti
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/lcd_controller.mpf
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/lcd_controller.v
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/lcd_testbench.v
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/transcript
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/vsim.wlf
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/wave.bmp
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/wave.do
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2/
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2/verilog.psm
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2/_primary.dat
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2/_primary.vhd
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2_altufm_parallel_bmm/
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2_altufm_parallel_bmm/verilog.psm
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2_altufm_parallel_bmm/_primary.dat
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2_altufm_parallel_bmm/_primary.vhd
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/divider/
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/divider/verilog.psm
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/divider/_primary.dat
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/divider/_primary.vhd
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/fsm/
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/fsm/verilog.psm
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/fsm/_primary.dat
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/fsm/_primary.vhd
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_controller/
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_controller/verilog.psm
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_controller/_primary.dat
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_controller/_primary.vhd
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_testbench/
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_testbench/verilog.psm
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_testbench/_primary.dat
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_testbench/_primary.vhd
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/_info
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(0).cnf.cdb
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(0).cnf.hdb
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(1).cnf.cdb
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(1).cnf.hdb
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(2).cnf.cdb
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(2).cnf.hdb
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(3).cnf.cdb
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(3).cnf.hdb
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(4).cnf.cdb
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(4).cnf.hdb
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.asm.qmsg
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.asm_labs.ddb
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.cbx.xml
CPLDLCD1602/LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.cmp.c

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