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文件名称:t1_bin2bcd

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2014-03-05
  • 文件大小：
    447.63kb
  • 已下载：
    0次
  • 提 供 者：
    宋****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

二进制转BCD的verilog程序，实现二进制数到BCD的转换，该程序具有节约FPGA的内部逻辑资源等特点-





























































Binary to BCD s verilog procedures to achieve binary number to BCD conversion, the program has an internal FPGA logic resources saving features
(系统自动生成,下载前可以参看下载内容)

下载文件列表

t1_bin2bcd/
t1_bin2bcd/bcd_encoder.bsf
t1_bin2bcd/bcd_encoder_modify.bsf
t1_bin2bcd/bcd_encoder_single.v
t1_bin2bcd/bcd_encoder_single.v.bak
t1_bin2bcd/bcd_encoder_single_modify.bsf
t1_bin2bcd/bcd_encoder_tb.v
t1_bin2bcd/bcd_encoder_tb.v.bak
t1_bin2bcd/db/
t1_bin2bcd/db/logic_util_heursitic.dat
t1_bin2bcd/db/prev_cmp_t1.qmsg
t1_bin2bcd/db/t1.(0).cnf.cdb
t1_bin2bcd/db/t1.(0).cnf.hdb
t1_bin2bcd/db/t1.(1).cnf.cdb
t1_bin2bcd/db/t1.(1).cnf.hdb
t1_bin2bcd/db/t1.(2).cnf.cdb
t1_bin2bcd/db/t1.(2).cnf.hdb
t1_bin2bcd/db/t1.(3).cnf.cdb
t1_bin2bcd/db/t1.(3).cnf.hdb
t1_bin2bcd/db/t1.amm.cdb
t1_bin2bcd/db/t1.asm.qmsg
t1_bin2bcd/db/t1.asm.rdb
t1_bin2bcd/db/t1.asm_labs.ddb
t1_bin2bcd/db/t1.cbx.xml
t1_bin2bcd/db/t1.cmp.bpm
t1_bin2bcd/db/t1.cmp.cdb
t1_bin2bcd/db/t1.cmp.hdb
t1_bin2bcd/db/t1.cmp.kpt
t1_bin2bcd/db/t1.cmp.logdb
t1_bin2bcd/db/t1.cmp.rdb
t1_bin2bcd/db/t1.cmp0.ddb
t1_bin2bcd/db/t1.cmp1.ddb
t1_bin2bcd/db/t1.cmp2.ddb
t1_bin2bcd/db/t1.cmp_merge.kpt
t1_bin2bcd/db/t1.db_info
t1_bin2bcd/db/t1.eda.qmsg
t1_bin2bcd/db/t1.fit.qmsg
t1_bin2bcd/db/t1.hier_info
t1_bin2bcd/db/t1.hif
t1_bin2bcd/db/t1.idb.cdb
t1_bin2bcd/db/t1.lpc.html
t1_bin2bcd/db/t1.lpc.rdb
t1_bin2bcd/db/t1.lpc.txt
t1_bin2bcd/db/t1.map.bpm
t1_bin2bcd/db/t1.map.cdb
t1_bin2bcd/db/t1.map.hdb
t1_bin2bcd/db/t1.map.kpt
t1_bin2bcd/db/t1.map.logdb
t1_bin2bcd/db/t1.map.qmsg
t1_bin2bcd/db/t1.map.rdb
t1_bin2bcd/db/t1.map_bb.cdb
t1_bin2bcd/db/t1.map_bb.hdb
t1_bin2bcd/db/t1.map_bb.logdb
t1_bin2bcd/db/t1.pre_map.cdb
t1_bin2bcd/db/t1.pre_map.hdb
t1_bin2bcd/db/t1.root_partition.map.reg_db.cdb
t1_bin2bcd/db/t1.routing.rdb
t1_bin2bcd/db/t1.rtlv.hdb
t1_bin2bcd/db/t1.rtlv_sg.cdb
t1_bin2bcd/db/t1.rtlv_sg_swap.cdb
t1_bin2bcd/db/t1.sgdiff.cdb
t1_bin2bcd/db/t1.sgdiff.hdb
t1_bin2bcd/db/t1.sld_design_entry.sci
t1_bin2bcd/db/t1.sld_design_entry_dsc.sci
t1_bin2bcd/db/t1.smart_action.txt
t1_bin2bcd/db/t1.sta.qmsg
t1_bin2bcd/db/t1.sta.rdb
t1_bin2bcd/db/t1.sta_cmp.8_slow.tdb
t1_bin2bcd/db/t1.syn_hier_info
t1_bin2bcd/db/t1.tis_db_list.ddb
t1_bin2bcd/db/t1.tmw_info
t1_bin2bcd/incremental_db/
t1_bin2bcd/incremental_db/compiled_partitions/
t1_bin2bcd/incremental_db/compiled_partitions/t1.db_info
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.cmp.cdb
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.cmp.dfp
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.cmp.hdb
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.cmp.kpt
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.cmp.logdb
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.cmp.rcfdb
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.map.cdb
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.map.dpi
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.map.hbdb.cdb
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.map.hbdb.hb_info
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.map.hbdb.hdb
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.map.hbdb.sig
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.map.hdb
t1_bin2bcd/incremental_db/compiled_partitions/t1.root_partition.map.kpt
t1_bin2bcd/incremental_db/README
t1_bin2bcd/simulation/
t1_bin2bcd/simulation/modelsim/
t1_bin2bcd/simulation/modelsim/modelsim.ini
t1_bin2bcd/simulation/modelsim/msim_transcript
t1_bin2bcd/simulation/modelsim/rtl_work/
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder/
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder/verilog.prw
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder/verilog.psm
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder/_primary.dat
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder/_primary.dbs
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder/_primary.vhd
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_modify/
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_modify/verilog.prw
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_modify/verilog.psm
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_modify/_primary.dat
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_modify/_primary.dbs
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_modify/_primary.vhd
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_single_modify/
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_single_modify/verilog.prw
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_single_modify/verilog.psm
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_single_modify/_primary.dat
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_single_modify/_primary.dbs
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_single_modify/_primary.vhd
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_tb/
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_tb/verilog.prw
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_tb/verilog.psm
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_tb/_primary.dat
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_tb/_primary.dbs
t1_bin2bcd/simulation/modelsim/rtl_work/bcd_encoder_tb/_primary.vhd
t1_bin2bcd/simulation/modelsim/rtl_work/_info
t1_bin2bcd/simulation/models

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