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文件名称:conv_encode

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [WORD]
  • 上传时间：
    2014-03-20
  • 文件大小：
    18.69mb
  • 已下载：
    0次
  • 提 供 者：
    郭***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

本设计是一个基于FPGA的咬尾卷积码编码器设计，要求使用verilog语言编写编码器模块，通过编译和综合，并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by contrast matlab and modelsim simulation results validate the design.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

2111303098-XXX.doc
conv_enc/conv.asm.rpt
conv_enc/conv.done
conv_enc/conv.eda.rpt
conv_enc/conv.fit.rpt
conv_enc/conv.fit.smsg
conv_enc/conv.fit.summary
conv_enc/conv.flow.rpt
conv_enc/conv.map.rpt
conv_enc/conv.map.smsg
conv_enc/conv.map.summary
conv_enc/conv.pin
conv_enc/conv.pof
conv_enc/conv.qpf
conv_enc/conv.qsf
conv_enc/conv.qws
conv_enc/conv.sof
conv_enc/conv.tan.rpt
conv_enc/conv.tan.summary
conv_enc/conv_nativelink_simulation.rpt
conv_enc/conv_top.v
conv_enc/conv_top.v.bak
conv_enc/conv_top_tb.v
conv_enc/conv_top_tb.v.bak
conv_enc/db/alt_u_div_s0f.tdf
conv_enc/db/conv.(0).cnf.cdb
conv_enc/db/conv.(0).cnf.hdb
conv_enc/db/conv.(1).cnf.cdb
conv_enc/db/conv.(1).cnf.hdb
conv_enc/db/conv.(2).cnf.cdb
conv_enc/db/conv.(2).cnf.hdb
conv_enc/db/conv.(3).cnf.cdb
conv_enc/db/conv.(3).cnf.hdb
conv_enc/db/conv.(4).cnf.cdb
conv_enc/db/conv.(4).cnf.hdb
conv_enc/db/conv.(5).cnf.cdb
conv_enc/db/conv.(5).cnf.hdb
conv_enc/db/conv.(6).cnf.cdb
conv_enc/db/conv.(6).cnf.hdb
conv_enc/db/conv.ae.hdb
conv_enc/db/conv.asm.qmsg
conv_enc/db/conv.asm.rdb
conv_enc/db/conv.asm_labs.ddb
conv_enc/db/conv.cbx.xml
conv_enc/db/conv.cmp.bpm
conv_enc/db/conv.cmp.cdb
conv_enc/db/conv.cmp.ecobp
conv_enc/db/conv.cmp.hdb
conv_enc/db/conv.cmp.kpt
conv_enc/db/conv.cmp.logdb
conv_enc/db/conv.cmp.rdb
conv_enc/db/conv.cmp.tdb
conv_enc/db/conv.cmp0.ddb
conv_enc/db/conv.cmp_merge.kpt
conv_enc/db/conv.db_info
conv_enc/db/conv.eco.cdb
conv_enc/db/conv.eda.qmsg
conv_enc/db/conv.fit.qmsg
conv_enc/db/conv.hier_info
conv_enc/db/conv.hif
conv_enc/db/conv.lpc.html
conv_enc/db/conv.lpc.rdb
conv_enc/db/conv.lpc.txt
conv_enc/db/conv.map.bpm
conv_enc/db/conv.map.cdb
conv_enc/db/conv.map.ecobp
conv_enc/db/conv.map.hdb
conv_enc/db/conv.map.kpt
conv_enc/db/conv.map.logdb
conv_enc/db/conv.map.qmsg
conv_enc/db/conv.map_bb.cdb
conv_enc/db/conv.map_bb.hdb
conv_enc/db/conv.map_bb.logdb
conv_enc/db/conv.pre_map.cdb
conv_enc/db/conv.pre_map.hdb
conv_enc/db/conv.rpp.qmsg
conv_enc/db/conv.rtlv.hdb
conv_enc/db/conv.rtlv_sg.cdb
conv_enc/db/conv.rtlv_sg_swap.cdb
conv_enc/db/conv.sgate.rvd
conv_enc/db/conv.sgate_sm.rvd
conv_enc/db/conv.sgdiff.cdb
conv_enc/db/conv.sgdiff.hdb
conv_enc/db/conv.sld_design_entry.sci
conv_enc/db/conv.sld_design_entry_dsc.sci
conv_enc/db/conv.smart_action.txt
conv_enc/db/conv.syn_hier_info
conv_enc/db/conv.tan.qmsg
conv_enc/db/conv.tis_db_list.ddb
conv_enc/db/conv.tmw_info
conv_enc/db/logic_util_heursitic.dat
conv_enc/db/lpm_divide_76m.tdf
conv_enc/db/prev_cmp_conv.asm.qmsg
conv_enc/db/prev_cmp_conv.eda.qmsg
conv_enc/db/prev_cmp_conv.fit.qmsg
conv_enc/db/prev_cmp_conv.map.qmsg
conv_enc/db/prev_cmp_conv.qmsg
conv_enc/db/prev_cmp_conv.tan.qmsg
conv_enc/db/sign_div_unsign_ckh.tdf
conv_enc/encode.v
conv_enc/encode.v.bak
conv_enc/incremental_db/compiled_partitions/conv.root_partition.cmp.cdb
conv_enc/incremental_db/compiled_partitions/conv.root_partition.cmp.dfp
conv_enc/incremental_db/compiled_partitions/conv.root_partition.cmp.hdb
conv_enc/incremental_db/compiled_partitions/conv.root_partition.cmp.kpt
conv_enc/incremental_db/compiled_partitions/conv.root_partition.cmp.logdb
conv_enc/incremental_db/compiled_partitions/conv.root_partition.cmp.rcfdb
conv_enc/incremental_db/compiled_partitions/conv.root_partition.cmp.re.rcfdb
conv_enc/incremental_db/compiled_partitions/conv.root_partition.map.cdb
conv_enc/incremental_db/compiled_partitions/conv.root_partition.map.dpi
conv_enc/incremental_db/compiled_partitions/conv.root_partition.map.hdb
conv_enc/incremental_db/compiled_partitions/conv.root_partition.map.kpt
conv_enc/incremental_db/README
conv_enc/input_ram.v
conv_enc/input_ram.v.bak
conv_enc/simulation/modelsim/conv.sft
conv_enc/simulation/modelsim/conv.vho
conv_enc/simulation/modelsim/conv_modelsim.xrf
conv_enc/simulation/modelsim/conv_run_msim_rtl_verilog.do
conv_enc/simulation/modelsim/conv_run_msim_rtl_verilog.do.bak
conv_enc/simulation/modelsim/conv_run_msim_rtl_verilog.do.bak1
conv_enc/simulation/modelsim/conv_run_msim_rtl_verilog.do.bak2
conv_enc/simulation/modelsim/conv_vhd.sdo
conv_enc/simulation/modelsim/modelsim.ini
conv_enc/simulation/modelsim/msim_transcript
conv_enc/simulation/modelsim/rtl_work/conv_top/verilog.prw
conv_enc/simulation/modelsim/rtl_work/conv_top/verilog.psm
conv_enc/simulation/modelsim/rtl_work/conv_top/_primary.dat
conv_enc/simulation/modelsim/rtl_work/conv_top/_primary.dbs
conv_enc/simulation/modelsim/rtl_work/conv_top/_primary.vhd
conv_enc/simulation/modelsim/rtl_work/conv_top_tb/verilog.prw
conv_enc/simulation/modelsim/rtl_work/conv_top_tb/verilog.psm
conv_enc/simulation/modelsim/rtl_work/conv_top_tb/_primary.dat
conv_enc/simulation/modelsim/rtl_work/conv_top_tb/_primary.dbs
conv_enc/simulation/modelsim/rtl_work/conv_top_tb/_primary.vhd
conv_enc/simulation/modelsim/rtl_work/encode/verilog.prw
conv_enc/simulation/modelsim/rtl_work/encode/verilog.psm
conv_enc/simulation/modelsim/rtl_work/encode/_primary.dat
conv_enc/simulation/modelsim/rtl_work/encode/_primary.dbs
conv_enc/simulation/modelsim/rtl_work/encode/_primary.vhd
conv_enc/simulation/modelsim/rtl_work/input_ram/verilog.prw
conv_enc/simulation/modelsim/rtl_work/input_ram/verilog.psm
con

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