文件名称:DE1-verilog
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- 上传时间:2014-03-23
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文件大小:11.35mb
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Altera公司推出最新开发板DE1。该资料为DE1的FPGA 代码,包括ADC,音频处理,视频输出等,供大家参考使用。-Altera Corporation introduced the latest development board DE1. The data for the DE1 FPGA code, including the ADC, audio processing, video output, etc., for your use and reference.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FPGA/DE1_SoC_ADC/.qsys_edit/filters.xml
FPGA/DE1_SoC_ADC/.qsys_edit/preferences.xml
FPGA/DE1_SoC_ADC/c5_pin_model_dump.txt
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.cdf
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.done
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.fit.smsg
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.fit.summary
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.jdi
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.map.smsg
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.map.summary
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.pin
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.qpf
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.qsf
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.qws
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.sdc
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.sof
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.sta.summary
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/DE1_SoC_QSYS.qip
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/DE1_SoC_QSYS.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_avalon_dc_fifo.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_avalon_st_pipeline_stage.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_irq_clock_crosser.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_master_agent.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_master_translator.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_traffic_limiter.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_reset_controller.sdc
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_reset_controller.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_reset_synchronizer.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_addr_router.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_addr_router_001.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_addr_router_002.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_altpll_0.qip
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_altpll_0.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cmd_xbar_demux.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cmd_xbar_demux_001.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cmd_xbar_demux_002.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cmd_xbar_mux.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu.ocp
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu.sdc
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_bht_ram.mif
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_dc_tag_ram.mif
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_ic_tag_ram.mif
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_jtag_debug_module_sysclk.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_jtag_debug_module_tck.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_jtag_debug_module_wrapper.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_mult_cell.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_ociram_default_contents.mif
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_oci_test_bench.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_rf_ram_a.mif
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_rf_ram_b.mif
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_test_bench.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_id_router.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_id_router_002.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_id_router_004.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_irq_mapper.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_jtag_uart.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_onchip_memory2.hex
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_onchip_memory2.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_rsp_xbar_demux_002.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_rsp_xbar_demux_004.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_rsp_xbar_mux.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_rsp_xbar_mux_001.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_rsp_xbar_mux_002.sv
FPGA/DE
FPGA/DE1_SoC_ADC/.qsys_edit/preferences.xml
FPGA/DE1_SoC_ADC/c5_pin_model_dump.txt
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.cdf
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.done
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.fit.smsg
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.fit.summary
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.jdi
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.map.smsg
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.map.summary
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.pin
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.qpf
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.qsf
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.qws
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.sdc
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.sof
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.sta.summary
FPGA/DE1_SoC_ADC/DE1_SoC_ADC.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/DE1_SoC_QSYS.qip
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/DE1_SoC_QSYS.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_avalon_dc_fifo.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_avalon_st_pipeline_stage.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_irq_clock_crosser.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_master_agent.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_master_translator.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_merlin_traffic_limiter.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_reset_controller.sdc
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_reset_controller.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/altera_reset_synchronizer.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_addr_router.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_addr_router_001.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_addr_router_002.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_altpll_0.qip
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_altpll_0.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cmd_xbar_demux.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cmd_xbar_demux_001.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cmd_xbar_demux_002.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cmd_xbar_mux.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu.ocp
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu.sdc
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_bht_ram.mif
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_dc_tag_ram.mif
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_ic_tag_ram.mif
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_jtag_debug_module_sysclk.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_jtag_debug_module_tck.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_jtag_debug_module_wrapper.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_mult_cell.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_ociram_default_contents.mif
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_oci_test_bench.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_rf_ram_a.mif
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_rf_ram_b.mif
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_cpu_test_bench.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_id_router.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_id_router_002.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_id_router_004.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_irq_mapper.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_jtag_uart.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_onchip_memory2.hex
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_onchip_memory2.v
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_rsp_xbar_demux_002.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_rsp_xbar_demux_004.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_rsp_xbar_mux.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_rsp_xbar_mux_001.sv
FPGA/DE1_SoC_ADC/DE1_SoC_QSYS/synthesis/submodules/DE1_SoC_QSYS_rsp_xbar_mux_002.sv
FPGA/DE
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