5/
5/Quartus/
5/Quartus/VGA_CTL.asm.rpt
5/Quartus/VGA_CTL.done
5/Quartus/VGA_CTL.dpf
5/Quartus/VGA_CTL.fit.rpt
5/Quartus/VGA_CTL.fit.smsg
5/Quartus/VGA_CTL.fit.summary
5/Quartus/VGA_CTL.flow.rpt
5/Quartus/VGA_CTL.map.rpt
5/Quartus/VGA_CTL.map.summary
5/Quartus/VGA_CTL.pin
5/Quartus/VGA_CTL.pof
5/Quartus/VGA_CTL.qpf
5/Quartus/VGA_CTL.qsf
5/Quartus/VGA_CTL.qws
5/Quartus/VGA_CTL.sof
5/Quartus/VGA_CTL.tan.rpt
5/Quartus/VGA_CTL.tan.summary
5/Quartus/db/
5/Quartus/db/VGA.db_info
5/Quartus/db/VGA.eco.cdb
5/Quartus/db/VGA.sld_design_entry.sci
5/Quartus/db/VGA_CTL.(0).cnf.cdb
5/Quartus/db/VGA_CTL.(0).cnf.hdb
5/Quartus/db/VGA_CTL.(1).cnf.cdb
5/Quartus/db/VGA_CTL.(1).cnf.hdb
5/Quartus/db/VGA_CTL.(2).cnf.cdb
5/Quartus/db/VGA_CTL.(2).cnf.hdb
5/Quartus/db/VGA_CTL.(3).cnf.cdb
5/Quartus/db/VGA_CTL.(3).cnf.hdb
5/Quartus/db/VGA_CTL.asm.qmsg
5/Quartus/db/VGA_CTL.asm_labs.ddb
5/Quartus/db/VGA_CTL.cbx.xml
5/Quartus/db/VGA_CTL.cmp.bpm
5/Quartus/db/VGA_CTL.cmp.cdb
5/Quartus/db/VGA_CTL.cmp.ecobp
5/Quartus/db/VGA_CTL.cmp.hdb
5/Quartus/db/VGA_CTL.cmp.kpt
5/Quartus/db/VGA_CTL.cmp.logdb
5/Quartus/db/VGA_CTL.cmp.rdb
5/Quartus/db/VGA_CTL.cmp.tdb
5/Quartus/db/VGA_CTL.cmp0.ddb
5/Quartus/db/VGA_CTL.cmp2.ddb
5/Quartus/db/VGA_CTL.cmp_merge.kpt
5/Quartus/db/VGA_CTL.db_info
5/Quartus/db/VGA_CTL.eco.cdb
5/Quartus/db/VGA_CTL.fit.qmsg
5/Quartus/db/VGA_CTL.hier_info
5/Quartus/db/VGA_CTL.hif
5/Quartus/db/VGA_CTL.lpc.html
5/Quartus/db/VGA_CTL.lpc.rdb
5/Quartus/db/VGA_CTL.lpc.txt
5/Quartus/db/VGA_CTL.map.bpm
5/Quartus/db/VGA_CTL.map.cdb
5/Quartus/db/VGA_CTL.map.ecobp
5/Quartus/db/VGA_CTL.map.hdb
5/Quartus/db/VGA_CTL.map.kpt
5/Quartus/db/VGA_CTL.map.logdb
5/Quartus/db/VGA_CTL.map.qmsg
5/Quartus/db/VGA_CTL.map_bb.cdb
5/Quartus/db/VGA_CTL.map_bb.hdb
5/Quartus/db/VGA_CTL.map_bb.logdb
5/Quartus/db/VGA_CTL.pre_map.cdb
5/Quartus/db/VGA_CTL.pre_map.hdb
5/Quartus/db/VGA_CTL.rtlv.hdb
5/Quartus/db/VGA_CTL.rtlv_sg.cdb
5/Quartus/db/VGA_CTL.rtlv_sg_swap.cdb
5/Quartus/db/VGA_CTL.sgdiff.cdb
5/Quartus/db/VGA_CTL.sgdiff.hdb
5/Quartus/db/VGA_CTL.sld_design_entry.sci
5/Quartus/db/VGA_CTL.sld_design_entry_dsc.sci
5/Quartus/db/VGA_CTL.syn_hier_info
5/Quartus/db/VGA_CTL.tan.qmsg
5/Quartus/db/VGA_CTL.tis_db_list.ddb
5/Quartus/db/VGA_CTL.tmw_info
5/Quartus/db/VGA_CTL_global_asgn_op.abo
5/Quartus/db/altsyncram_3881.tdf
5/Quartus/db/prev_cmp_VGA_CTL.asm.qmsg
5/Quartus/db/prev_cmp_VGA_CTL.fit.qmsg
5/Quartus/db/prev_cmp_VGA_CTL.map.qmsg
5/Quartus/db/prev_cmp_VGA_CTL.qmsg
5/Quartus/db/prev_cmp_VGA_CTL.tan.qmsg
5/Quartus/incremental_db/
5/Quartus/incremental_db/README
5/Quartus/incremental_db/compiled_partitions/
5/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.cmp.atm
5/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.cmp.dfp
5/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.cmp.hdbx
5/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.cmp.kpt
5/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.cmp.logdb
5/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.cmp.rcf
5/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.map.atm
5/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.map.dpi
5/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.map.hdbx
5/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.map.kpt
5/Testbench/
5/Testbench/VGA_tb.v
5/Testbench/altera_mf.v
5/modelsim/
5/modelsim/VGA.cr.mti
5/modelsim/VGA.mpf
5/modelsim/transcript
5/modelsim/vga.do
5/modelsim/vsim.wlf
5/modelsim/work/
5/modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/
5/modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
5/modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
5/modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
5/modelsim/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/
5/modelsim/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
5/modelsim/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
5/modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/
5/modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
5/modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
5/modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.asm
5/modelsim/work/@m@f_cycloneiii_pll/
5/modelsim/work/@m@f_cycloneiii_pll/_primary.dat
5/modelsim/work/@m@f_cycloneiii_pll/_primary.vhd
5/modelsim/work/@m@f_pll_reg/
5/modelsim/work/@m@f_pll_reg/_primary.dat
5/modelsim/work/@m@f_pll_reg/_primary.vhd
5/modelsim/work/@m@f_stratix_pll/
5/modelsim/work/@m@f_stratix_pll/_primary.dat
5/modelsim/work/@m@f_stratix_pll/_primary.vhd
5/modelsim/work/@m@f_stratixii_pll/
5/modelsim/work/@m@f_stratixii_pll/_primary.dat
5/modelsim/work/@m@f_stratixii_pll/_primary.vhd
5/modelsim/work/@m@f_stratixiii_pll/
5/modelsim/work/@m@f_stratixiii_pll/_primary.dat
5/modelsim/work/@m@f_stratixiii_pll/_primary.vhd
5/modelsim/work/@r@o@m/
5/modelsim/work/@r@o@m/_primary.dat
5/modelsim/work/@r@o@m/_primary.vhd
5/model