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文件名称:Example-b8-6

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [WORD]
  • 上传时间：
    2014-04-06
  • 文件大小：
    121.16kb
  • 已下载：
    0次
  • 提 供 者：
    波*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Synplify Pro综合流程序仿真，注：本范例同时提供Verilog和VHDL两种语言版本，请读者根据习惯选用不同的源代码进行操作。-Synplify Pro comprehensive process simulation (note: this example provides two Verilog and VHDL language version at the same time, please choose the different readers according to the habits of the source code.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Example-b8-6/source/mixed/verilog/mux.vhd
Example-b8-6/source/mixed/verilog/mux21.v
Example-b8-6/source/mixed/verilog/reg8.vhd
Example-b8-6/source/mixed/verilog/rotate.vhd
Example-b8-6/source/mixed/verilog/top.v
Example-b8-6/source/mixed/vhdl/mux.v
Example-b8-6/source/mixed/vhdl/mux21.vhd
Example-b8-6/source/mixed/vhdl/reg8.v
Example-b8-6/source/mixed/vhdl/rotate.v
Example-b8-6/source/mixed/vhdl/top.vhd
Example-b8-6/source/verilog/ALU.V
Example-b8-6/source/verilog/HDL_DEMO.V
Example-b8-6/source/VHDL/ALU.VHD
Example-b8-6/source/VHDL/HDL_DEMO.VHD
Example-b8-6/Synplify_Pro/ALU_Syn_2.prd
Example-b8-6/Synplify_Pro/ALU_Syn_2.prj
Example-b8-6/Synplify_Pro/ALU_Syn_demo.prd
Example-b8-6/Synplify_Pro/ALU_Syn_demo.prj
Example-b8-6/Synplify_Pro/ALU_Syn_demo.sdc
Example-b8-6/Synplify_Pro/Mix_src.prd
Example-b8-6/Synplify_Pro/Mix_src_vhdl.prd
Example-b8-6/Synplify_Pro/Mix_src_vhdl.prj
Example-b8-6/Synplify_Pro/Mix_src_vlog.prd
Example-b8-6/Synplify_Pro/Mix_src_vlog.prj
Example-b8-6/Synplify_Pro/MyWorkspace.prd
Example-b8-6/Synplify_Pro/MyWorkspace.prj
Example-b8-6/Synplify_Pro/rev_1/ALU.fse
Example-b8-6/Synplify_Pro/rev_1/ALU.srd
Example-b8-6/Synplify_Pro/rev_1/ALU.srm
Example-b8-6/Synplify_Pro/rev_1/ALU.srr
Example-b8-6/Synplify_Pro/rev_1/ALU.srs
Example-b8-6/Synplify_Pro/rev_1/ALU.sxr
Example-b8-6/Synplify_Pro/rev_1/ALU.tcl
Example-b8-6/Synplify_Pro/rev_1/ALU.tlg
Example-b8-6/Synplify_Pro/rev_1/ALU.vqm
Example-b8-6/Synplify_Pro/rev_1/ALU.xrf
Example-b8-6/Synplify_Pro/rev_1/ALU_cons.tcl
Example-b8-6/Synplify_Pro/rev_1/ALU_rm.tcl
Example-b8-6/Synplify_Pro/rev_1/AutoConstraint_alu.sdc
Example-b8-6/Synplify_Pro/rev_1/fsmviewer.fsm
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.fse
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.srd
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.srm
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.srr
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.srs
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.sxr
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.ta
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.taq
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.tcl
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.tlg
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.vqm
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO.xrf
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO_cons.tcl
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO_rm.tcl
Example-b8-6/Synplify_Pro/rev_1/HDL_DEMO_ta.srm
Example-b8-6/Synplify_Pro/rev_1/syntmp/ALU.plg
Example-b8-6/Synplify_Pro/rev_1/syntmp/HDL_DEMO.plg
Example-b8-6/Synplify_Pro/rev_2/.recordref
Example-b8-6/Synplify_Pro/rev_2/AutoConstraint_top.sdc
Example-b8-6/Synplify_Pro/rev_2/layer0.tlg
Example-b8-6/Synplify_Pro/rev_2/layer1.tlg
Example-b8-6/Synplify_Pro/rev_2/layer2.tlg
Example-b8-6/Synplify_Pro/rev_2/stderr.log
Example-b8-6/Synplify_Pro/rev_2/stdout.log
Example-b8-6/Synplify_Pro/rev_2/syntmp/top.plg
Example-b8-6/Synplify_Pro/rev_2/top.fse
Example-b8-6/Synplify_Pro/rev_2/top.srd
Example-b8-6/Synplify_Pro/rev_2/top.srm
Example-b8-6/Synplify_Pro/rev_2/top.srr
Example-b8-6/Synplify_Pro/rev_2/top.srs
Example-b8-6/Synplify_Pro/rev_2/top.sxr
Example-b8-6/Synplify_Pro/rev_2/top.tcl
Example-b8-6/Synplify_Pro/rev_2/top.vqm
Example-b8-6/Synplify_Pro/rev_2/top.xrf
Example-b8-6/Synplify_Pro/rev_2/top_cons.tcl
Example-b8-6/Synplify_Pro/rev_2/top_rm.tcl
Example-b8-6/Synplify_Pro/rev_3/.recordref
Example-b8-6/Synplify_Pro/rev_3/layer0.tlg
Example-b8-6/Synplify_Pro/rev_3/layer1.tlg
Example-b8-6/Synplify_Pro/rev_3/layer2.tlg
Example-b8-6/Synplify_Pro/rev_3/stderr.log
Example-b8-6/Synplify_Pro/rev_3/stdout.log
Example-b8-6/Synplify_Pro/rev_3/syntmp/mux.plg
Example-b8-6/Synplify_Pro/rev_3/syntmp/rotate.plg
Example-b8-6/Synplify_Pro/rev_3/syntmp/top.plg
Example-b8-6/Synplify_Pro/rev_3/syntmp/top1.plg
Example-b8-6/Synplify_Pro/rev_3/top1.fse
Example-b8-6/Synplify_Pro/rev_3/top1.srd
Example-b8-6/Synplify_Pro/rev_3/top1.srm
Example-b8-6/Synplify_Pro/rev_3/top1.srr
Example-b8-6/Synplify_Pro/rev_3/top1.srs
Example-b8-6/Synplify_Pro/rev_3/top1.sxr
Example-b8-6/Synplify_Pro/rev_3/top1.tcl
Example-b8-6/Synplify_Pro/rev_3/top1.vqm
Example-b8-6/Synplify_Pro/rev_3/top1.xrf
Example-b8-6/Synplify_Pro/rev_3/top1_cons.tcl
Example-b8-6/Synplify_Pro/rev_3/top1_rm.tcl
Example-b8-6/Synplify_Pro/source/mixed/verilog/mux.vhd
Example-b8-6/Synplify_Pro/source/mixed/verilog/mux21.v
Example-b8-6/Synplify_Pro/source/mixed/verilog/reg8.vhd
Example-b8-6/Synplify_Pro/source/mixed/verilog/rotate.vhd
Example-b8-6/Synplify_Pro/source/mixed/verilog/top.v
Example-b8-6/Synplify_Pro/source/mixed/vhdl/mux.v
Example-b8-6/Synplify_Pro/source/mixed/vhdl/mux21.vhd
Example-b8-6/Synplify_Pro/source/mixed/vhdl/reg8.v
Example-b8-6/Synplify_Pro/source/mixed/vhdl/rotate.v
Example-b8-6/Synplify_Pro/source/mixed/vhdl/top.vhd
Example-b8-6/Synplify_Pro/source/verilog/ALU.V
Example-b8-6/Synplify_Pro/source/verilog/HDL_DEMO.V
Example-b8-6/Synplify_Pro/source/VHDL/ALU.VHD
Example-b8-6/Synplify_Pro/source/VHDL/HDL_DEMO.VHD
Example-b8-6/示例说明.doc
Example-b8-6/Synplify_Pro/source/mixed/verilog
Example-b8-6/Synplify_Pro/source/mixed/vhdl
Example-b8-6/source/mixed/verilog
Example-b8-6/source/mixed/vhdl
Example-b8-6/Synplify_Pro/rev_1/syntmp
Example-b8-6/Synplify_Pro/

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