文件名称:FSK
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- 上传时间:2014-04-09
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文件大小:785kb
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已下载:1次
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FPGA实现FSK调制,带Modelsim仿真,实际系统测试通过,载波信号,信号频率等可调。-FPGA implementation FSK modulation with Modelsim simulation, the actual system test, the carrier signal, the signal frequency is adjustable.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FSK/
FSK/Code/
FSK/Code/DDS.v
FSK/Code/FSK.v
FSK/Code/FSK_tb.v
FSK/Code/FSK_tb.v.bak
FSK/Code/Fs_Gen.v
FSK/Code/m.v
FSK/Code/SIN14Bit.mif
FSK/Code/SinRom.v
FSK/Modelsim/
FSK/Modelsim/FSK.cr.mti
FSK/Modelsim/FSK.mpf
FSK/Modelsim/SIN14Bit.mif
FSK/Modelsim/SIN14Bit.ver
FSK/Modelsim/vsim.wlf
FSK/Modelsim/work/
FSK/Modelsim/work/@d@d@s/
FSK/Modelsim/work/@d@d@s/verilog.asm
FSK/Modelsim/work/@d@d@s/verilog.rw
FSK/Modelsim/work/@d@d@s/_primary.dat
FSK/Modelsim/work/@d@d@s/_primary.dbs
FSK/Modelsim/work/@d@d@s/_primary.vhd
FSK/Modelsim/work/@f@s@k/
FSK/Modelsim/work/@f@s@k/verilog.asm
FSK/Modelsim/work/@f@s@k/verilog.rw
FSK/Modelsim/work/@f@s@k/_primary.dat
FSK/Modelsim/work/@f@s@k/_primary.dbs
FSK/Modelsim/work/@f@s@k/_primary.vhd
FSK/Modelsim/work/@sin@rom/
FSK/Modelsim/work/@sin@rom/verilog.asm
FSK/Modelsim/work/@sin@rom/verilog.rw
FSK/Modelsim/work/@sin@rom/_primary.dat
FSK/Modelsim/work/@sin@rom/_primary.dbs
FSK/Modelsim/work/@sin@rom/_primary.vhd
FSK/Modelsim/work/fs_@gen/
FSK/Modelsim/work/fs_@gen/verilog.asm
FSK/Modelsim/work/fs_@gen/verilog.rw
FSK/Modelsim/work/fs_@gen/_primary.dat
FSK/Modelsim/work/fs_@gen/_primary.dbs
FSK/Modelsim/work/fs_@gen/_primary.vhd
FSK/Modelsim/work/m_tb/
FSK/Modelsim/work/m_tb/verilog.asm
FSK/Modelsim/work/m_tb/verilog.rw
FSK/Modelsim/work/m_tb/_primary.dat
FSK/Modelsim/work/m_tb/_primary.dbs
FSK/Modelsim/work/m_tb/_primary.vhd
FSK/Modelsim/work/wsj/
FSK/Modelsim/work/wsj/verilog.asm
FSK/Modelsim/work/wsj/verilog.rw
FSK/Modelsim/work/wsj/_primary.dat
FSK/Modelsim/work/wsj/_primary.dbs
FSK/Modelsim/work/wsj/_primary.vhd
FSK/Modelsim/work/_info
FSK/Modelsim/work/_temp/
FSK/Modelsim/work/_vmake
FSK/Code/
FSK/Code/DDS.v
FSK/Code/FSK.v
FSK/Code/FSK_tb.v
FSK/Code/FSK_tb.v.bak
FSK/Code/Fs_Gen.v
FSK/Code/m.v
FSK/Code/SIN14Bit.mif
FSK/Code/SinRom.v
FSK/Modelsim/
FSK/Modelsim/FSK.cr.mti
FSK/Modelsim/FSK.mpf
FSK/Modelsim/SIN14Bit.mif
FSK/Modelsim/SIN14Bit.ver
FSK/Modelsim/vsim.wlf
FSK/Modelsim/work/
FSK/Modelsim/work/@d@d@s/
FSK/Modelsim/work/@d@d@s/verilog.asm
FSK/Modelsim/work/@d@d@s/verilog.rw
FSK/Modelsim/work/@d@d@s/_primary.dat
FSK/Modelsim/work/@d@d@s/_primary.dbs
FSK/Modelsim/work/@d@d@s/_primary.vhd
FSK/Modelsim/work/@f@s@k/
FSK/Modelsim/work/@f@s@k/verilog.asm
FSK/Modelsim/work/@f@s@k/verilog.rw
FSK/Modelsim/work/@f@s@k/_primary.dat
FSK/Modelsim/work/@f@s@k/_primary.dbs
FSK/Modelsim/work/@f@s@k/_primary.vhd
FSK/Modelsim/work/@sin@rom/
FSK/Modelsim/work/@sin@rom/verilog.asm
FSK/Modelsim/work/@sin@rom/verilog.rw
FSK/Modelsim/work/@sin@rom/_primary.dat
FSK/Modelsim/work/@sin@rom/_primary.dbs
FSK/Modelsim/work/@sin@rom/_primary.vhd
FSK/Modelsim/work/fs_@gen/
FSK/Modelsim/work/fs_@gen/verilog.asm
FSK/Modelsim/work/fs_@gen/verilog.rw
FSK/Modelsim/work/fs_@gen/_primary.dat
FSK/Modelsim/work/fs_@gen/_primary.dbs
FSK/Modelsim/work/fs_@gen/_primary.vhd
FSK/Modelsim/work/m_tb/
FSK/Modelsim/work/m_tb/verilog.asm
FSK/Modelsim/work/m_tb/verilog.rw
FSK/Modelsim/work/m_tb/_primary.dat
FSK/Modelsim/work/m_tb/_primary.dbs
FSK/Modelsim/work/m_tb/_primary.vhd
FSK/Modelsim/work/wsj/
FSK/Modelsim/work/wsj/verilog.asm
FSK/Modelsim/work/wsj/verilog.rw
FSK/Modelsim/work/wsj/_primary.dat
FSK/Modelsim/work/wsj/_primary.dbs
FSK/Modelsim/work/wsj/_primary.vhd
FSK/Modelsim/work/_info
FSK/Modelsim/work/_temp/
FSK/Modelsim/work/_vmake
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