文件名称:BPSK
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- 上传时间:2014-04-09
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文件大小:1.04mb
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已下载:2次
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FPGA实现BPSK调制,带Modelsim仿真,实际系统测试通过,载波信号,调制波信号频率可调-FPGA implementation BPSK modulation with Modelsim simulation, the actual system test, the carrier signal, modulated wave signal frequency adjustable
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下载文件列表
BPSK/
BPSK/Code/
BPSK/Code/BPSK.v
BPSK/Code/BPSK_tb.v
BPSK/Code/BPSK_tb.v.bak
BPSK/Code/Fs_Gen.v
BPSK/Code/m.v
BPSK/Code/SIN14Bit.mif
BPSK/Code/SinRom.v
BPSK/Modelsim/
BPSK/Modelsim/BPSK.cr.mti
BPSK/Modelsim/BPSK.mpf
BPSK/Modelsim/SIN14Bit.mif
BPSK/Modelsim/SIN14Bit.ver
BPSK/Modelsim/vsim.wlf
BPSK/Modelsim/work/
BPSK/Modelsim/work/@b@p@s@k/
BPSK/Modelsim/work/@b@p@s@k/verilog.asm
BPSK/Modelsim/work/@b@p@s@k/verilog.rw
BPSK/Modelsim/work/@b@p@s@k/_primary.dat
BPSK/Modelsim/work/@b@p@s@k/_primary.dbs
BPSK/Modelsim/work/@b@p@s@k/_primary.vhd
BPSK/Modelsim/work/@sin@rom/
BPSK/Modelsim/work/@sin@rom/verilog.asm
BPSK/Modelsim/work/@sin@rom/verilog.rw
BPSK/Modelsim/work/@sin@rom/_primary.dat
BPSK/Modelsim/work/@sin@rom/_primary.dbs
BPSK/Modelsim/work/@sin@rom/_primary.vhd
BPSK/Modelsim/work/fs_@gen/
BPSK/Modelsim/work/fs_@gen/verilog.asm
BPSK/Modelsim/work/fs_@gen/verilog.rw
BPSK/Modelsim/work/fs_@gen/_primary.dat
BPSK/Modelsim/work/fs_@gen/_primary.dbs
BPSK/Modelsim/work/fs_@gen/_primary.vhd
BPSK/Modelsim/work/m_tb/
BPSK/Modelsim/work/m_tb/verilog.asm
BPSK/Modelsim/work/m_tb/verilog.rw
BPSK/Modelsim/work/m_tb/_primary.dat
BPSK/Modelsim/work/m_tb/_primary.dbs
BPSK/Modelsim/work/m_tb/_primary.vhd
BPSK/Modelsim/work/wsj/
BPSK/Modelsim/work/wsj/verilog.asm
BPSK/Modelsim/work/wsj/verilog.rw
BPSK/Modelsim/work/wsj/_primary.dat
BPSK/Modelsim/work/wsj/_primary.dbs
BPSK/Modelsim/work/wsj/_primary.vhd
BPSK/Modelsim/work/_info
BPSK/Modelsim/work/_temp/
BPSK/Modelsim/work/_vmake
BPSK/Code/
BPSK/Code/BPSK.v
BPSK/Code/BPSK_tb.v
BPSK/Code/BPSK_tb.v.bak
BPSK/Code/Fs_Gen.v
BPSK/Code/m.v
BPSK/Code/SIN14Bit.mif
BPSK/Code/SinRom.v
BPSK/Modelsim/
BPSK/Modelsim/BPSK.cr.mti
BPSK/Modelsim/BPSK.mpf
BPSK/Modelsim/SIN14Bit.mif
BPSK/Modelsim/SIN14Bit.ver
BPSK/Modelsim/vsim.wlf
BPSK/Modelsim/work/
BPSK/Modelsim/work/@b@p@s@k/
BPSK/Modelsim/work/@b@p@s@k/verilog.asm
BPSK/Modelsim/work/@b@p@s@k/verilog.rw
BPSK/Modelsim/work/@b@p@s@k/_primary.dat
BPSK/Modelsim/work/@b@p@s@k/_primary.dbs
BPSK/Modelsim/work/@b@p@s@k/_primary.vhd
BPSK/Modelsim/work/@sin@rom/
BPSK/Modelsim/work/@sin@rom/verilog.asm
BPSK/Modelsim/work/@sin@rom/verilog.rw
BPSK/Modelsim/work/@sin@rom/_primary.dat
BPSK/Modelsim/work/@sin@rom/_primary.dbs
BPSK/Modelsim/work/@sin@rom/_primary.vhd
BPSK/Modelsim/work/fs_@gen/
BPSK/Modelsim/work/fs_@gen/verilog.asm
BPSK/Modelsim/work/fs_@gen/verilog.rw
BPSK/Modelsim/work/fs_@gen/_primary.dat
BPSK/Modelsim/work/fs_@gen/_primary.dbs
BPSK/Modelsim/work/fs_@gen/_primary.vhd
BPSK/Modelsim/work/m_tb/
BPSK/Modelsim/work/m_tb/verilog.asm
BPSK/Modelsim/work/m_tb/verilog.rw
BPSK/Modelsim/work/m_tb/_primary.dat
BPSK/Modelsim/work/m_tb/_primary.dbs
BPSK/Modelsim/work/m_tb/_primary.vhd
BPSK/Modelsim/work/wsj/
BPSK/Modelsim/work/wsj/verilog.asm
BPSK/Modelsim/work/wsj/verilog.rw
BPSK/Modelsim/work/wsj/_primary.dat
BPSK/Modelsim/work/wsj/_primary.dbs
BPSK/Modelsim/work/wsj/_primary.vhd
BPSK/Modelsim/work/_info
BPSK/Modelsim/work/_temp/
BPSK/Modelsim/work/_vmake
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