uart_lcd/designer/impl1/designer.log
uart_lcd/designer/impl1/designer_synth_check.log
uart_lcd/designer/impl1/gen.ide_des
uart_lcd/designer/impl1/lcd.ide_des
uart_lcd/designer/impl1/rec.ide_des
uart_lcd/designer/impl1/send.ide_des
uart_lcd/designer/impl1/top.ide_des
uart_lcd/designer/impl1/uart_test.adb
uart_lcd/designer/impl1/uart_test.dtf/verify.log
uart_lcd/designer/impl1/uart_test.ide_des
uart_lcd/designer/impl1/uart_test.pdb
uart_lcd/designer/impl1/uart_test.pdb.depends
uart_lcd/designer/impl1/uart_test.tcl
uart_lcd/designer/impl1/uart_test_1.ide_des
uart_lcd/designer/impl1/uart_test_1_fp/$$FlashPro_10619.L$$
uart_lcd/designer/impl1/uart_test_1_fp/uart_test.log
uart_lcd/designer/impl1/uart_test_1_fp/uart_test.pro
uart_lcd/designer/impl1/uart_test_1_fp_1/$$FlashPro_10619.L$$
uart_lcd/designer/impl1/uart_test_1_fp_1/uart_test.log
uart_lcd/designer/impl1/uart_test_1_fp_1/uart_test.pro
uart_lcd/designer/impl1/uart_test_1_fp_2/$$FlashPro_10619.L$$
uart_lcd/designer/impl1/uart_test_1_fp_2/uart_test.log
uart_lcd/designer/impl1/uart_test_1_fp_2/uart_test.pro
uart_lcd/designer/impl1/uart_test_1_fp_3/$$FlashPro_10619.L$$
uart_lcd/designer/impl1/uart_test_1_fp_3/uart_test.log
uart_lcd/designer/impl1/uart_test_1_fp_3/uart_test.pro
uart_lcd/designer/impl1/uart_test_1_fp_4/$$FlashPro_10619.L$$
uart_lcd/designer/impl1/uart_test_1_fp_4/uart_test.log
uart_lcd/designer/impl1/uart_test_1_fp_4/uart_test.pro
uart_lcd/designer/impl1/uart_test_1_fp_5/$$FlashPro_10619.L$$
uart_lcd/designer/impl1/uart_test_1_fp_5/uart_test.log
uart_lcd/designer/impl1/uart_test_1_fp_5/uart_test.pro
uart_lcd/designer/impl1/uart_test_1_fp_6/$$FlashPro_10619.L$$
uart_lcd/designer/impl1/uart_test_1_fp_6/uart_test.log
uart_lcd/designer/impl1/uart_test_1_fp_6/uart_test.pro
uart_lcd/designer/impl1/uart_test_fp/$$FlashPro_10619.L$$
uart_lcd/designer/impl1/uart_test_fp/uart_test.log
uart_lcd/designer/impl1/uart_test_fp/uart_test.pro
uart_lcd/hdl/gen.v
uart_lcd/hdl/lcd.v
uart_lcd/hdl/pl.v
uart_lcd/hdl/rec.v
uart_lcd/hdl/send.v
uart_lcd/hdl/top.v
uart_lcd/hdl/uart_test.v
uart_lcd/simulation/c3f5493e-7961-4b1e-ae12-61c5799f2ab5.tmp
uart_lcd/simulation/modelsim.ini
uart_lcd/simulation/modelsim.ini.sav
uart_lcd/smartgen/s6c4.xml
uart_lcd/smartgen/smartgen.aws
uart_lcd/synthesis/.recordref_modgen
uart_lcd/synthesis/backup/uart_test.srr
uart_lcd/synthesis/dm/uart_test.xdm
uart_lcd/synthesis/identify.log
uart_lcd/synthesis/run_options.txt
uart_lcd/synthesis/scratchproject.prs
uart_lcd/synthesis/stdout.log
uart_lcd/synthesis/synlog/uart_test_Fusion_Mapper.srr
uart_lcd/synthesis/synlog/uart_test_Fusion_Mapper.srr_Min
uart_lcd/synthesis/synlog/uart_test_Fusion_Mapper.szr
uart_lcd/synthesis/syntmp/closed.png
uart_lcd/synthesis/syntmp/cmdrec_compiler.log
uart_lcd/synthesis/syntmp/cmdrec_fusion_mapper.log
uart_lcd/synthesis/syntmp/open.png
uart_lcd/synthesis/syntmp/uart_test.msg
uart_lcd/synthesis/syntmp/uart_test.plg
uart_lcd/synthesis/syntmp/uart_test_flink.htm
uart_lcd/synthesis/syntmp/uart_test_srr.htm
uart_lcd/synthesis/syntmp/uart_test_toc.htm
uart_lcd/synthesis/traplog.tlg
uart_lcd/synthesis/uart_test.areasrr
uart_lcd/synthesis/uart_test.edn
uart_lcd/synthesis/uart_test.fse
uart_lcd/synthesis/uart_test.htm
uart_lcd/synthesis/uart_test.map
uart_lcd/synthesis/uart_test.pdc
uart_lcd/synthesis/uart_test.sdf
uart_lcd/synthesis/uart_test.so
uart_lcd/synthesis/uart_test.srd
uart_lcd/synthesis/uart_test.srl
uart_lcd/synthesis/uart_test.srm
uart_lcd/synthesis/uart_test.srr
uart_lcd/synthesis/uart_test.srs
uart_lcd/synthesis/uart_test.szr
uart_lcd/synthesis/uart_test.tlg
uart_lcd/synthesis/uart_test_drc.rpt
uart_lcd/synthesis/uart_test_sdc.sdc
uart_lcd/synthesis/uart_test_syn.prj
uart_lcd/uart_lcd.prj
uart_lcd/viewdraw/vf/project.lst
uart_lcd/viewdraw/viewdraw.ini
uart_lcd/designer/impl1/simulation
uart_lcd/designer/impl1/uart_test.dtf
uart_lcd/designer/impl1/uart_test_1_fp
uart_lcd/designer/impl1/uart_test_1_fp_1
uart_lcd/designer/impl1/uart_test_1_fp_2
uart_lcd/designer/impl1/uart_test_1_fp_3
uart_lcd/designer/impl1/uart_test_1_fp_4
uart_lcd/designer/impl1/uart_test_1_fp_5
uart_lcd/designer/impl1/uart_test_1_fp_6
uart_lcd/designer/impl1/uart_test_fp
uart_lcd/designer/impl1
uart_lcd/synthesis/backup
uart_lcd/synthesis/coreip
uart_lcd/synthesis/dm
uart_lcd/synthesis/synlog
uart_lcd/synthesis/syntmp
uart_lcd/viewdraw/sch
uart_lcd/viewdraw/sym
uart_lcd/viewdraw/vf
uart_lcd/viewdraw/wir
uart_lcd/component
uart_lcd/constraint
uart_lcd/coreconsole
uart_lcd/designer
uart_lcd/hdl
uart_lcd/phy_synthesis
uart_lcd/simulation
uart_lcd/smartgen
uart_lcd/stimulus
uart_lcd/synthesis
uart_lcd/viewdraw
uart_lcd