文件名称:asyn-fifo
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- 上传时间:2014-04-25
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文件大小:183.21kb
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功能就是一个FIFO,first in first out!避免跨时钟域的亚稳态-Function is a FIFO, first in first out! To avoid the cross clock domain metastable
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下载文件列表
asyn fifo/
asyn fifo/db/
asyn fifo/db/FIFO.db_info
asyn fifo/db/FIFO.sld_design_entry.sci
asyn fifo/db/logic_util_heursitic.dat
asyn fifo/db/prev_cmp_FIFO.qmsg
asyn fifo/FIFO.asm.rpt
asyn fifo/FIFO.done
asyn fifo/FIFO.eda.rpt
asyn fifo/FIFO.fit.rpt
asyn fifo/FIFO.fit.summary
asyn fifo/FIFO.flow.rpt
asyn fifo/FIFO.jdi
asyn fifo/FIFO.map.rpt
asyn fifo/FIFO.map.summary
asyn fifo/FIFO.pin
asyn fifo/FIFO.qpf
asyn fifo/FIFO.qsf
asyn fifo/FIFO.qws
asyn fifo/FIFO.sof
asyn fifo/FIFO.sta.rpt
asyn fifo/FIFO.sta.summary
asyn fifo/FIFO.v
asyn fifo/FIFO.v.bak
asyn fifo/fifo_ctrl.qip
asyn fifo/FIFO_nativelink_simulation.rpt
asyn fifo/greybox_tmp/
asyn fifo/greybox_tmp/cbx_args.txt
asyn fifo/incremental_db/
asyn fifo/incremental_db/compiled_partitions/
asyn fifo/incremental_db/compiled_partitions/FIFO.db_info
asyn fifo/incremental_db/README
asyn fifo/simulation/
asyn fifo/simulation/modelsim/
asyn fifo/simulation/modelsim/FIFO.sft
asyn fifo/simulation/modelsim/FIFO.vo
asyn fifo/simulation/modelsim/FIFO.vt
asyn fifo/simulation/modelsim/FIFO.vt.bak
asyn fifo/simulation/modelsim/FIFO_7_1200mv_0c_slow.vo
asyn fifo/simulation/modelsim/FIFO_7_1200mv_0c_v_slow.sdo
asyn fifo/simulation/modelsim/FIFO_7_1200mv_85c_slow.vo
asyn fifo/simulation/modelsim/FIFO_7_1200mv_85c_v_slow.sdo
asyn fifo/simulation/modelsim/FIFO_min_1200mv_0c_fast.vo
asyn fifo/simulation/modelsim/FIFO_min_1200mv_0c_v_fast.sdo
asyn fifo/simulation/modelsim/FIFO_modelsim.xrf
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak1
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak2
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak3
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak4
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak5
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak6
asyn fifo/simulation/modelsim/FIFO_v.sdo
asyn fifo/simulation/modelsim/msim_transcript
asyn fifo/simulation/modelsim/rtl_work/
asyn fifo/simulation/modelsim/rtl_work/@f@i@f@o/
asyn fifo/simulation/modelsim/rtl_work/@f@i@f@o/verilog.prw
asyn fifo/simulation/modelsim/rtl_work/@f@i@f@o/verilog.psm
asyn fifo/simulation/modelsim/rtl_work/@f@i@f@o/_primary.dat
asyn fifo/simulation/modelsim/rtl_work/@f@i@f@o/_primary.dbs
asyn fifo/simulation/modelsim/rtl_work/@f@i@f@o/_primary.vhd
asyn fifo/simulation/modelsim/rtl_work/_info
asyn fifo/simulation/modelsim/rtl_work/_temp/
asyn fifo/simulation/modelsim/rtl_work/_vmake
asyn fifo/simulation/modelsim/vsim.wlf
asyn fifo/db/
asyn fifo/db/FIFO.db_info
asyn fifo/db/FIFO.sld_design_entry.sci
asyn fifo/db/logic_util_heursitic.dat
asyn fifo/db/prev_cmp_FIFO.qmsg
asyn fifo/FIFO.asm.rpt
asyn fifo/FIFO.done
asyn fifo/FIFO.eda.rpt
asyn fifo/FIFO.fit.rpt
asyn fifo/FIFO.fit.summary
asyn fifo/FIFO.flow.rpt
asyn fifo/FIFO.jdi
asyn fifo/FIFO.map.rpt
asyn fifo/FIFO.map.summary
asyn fifo/FIFO.pin
asyn fifo/FIFO.qpf
asyn fifo/FIFO.qsf
asyn fifo/FIFO.qws
asyn fifo/FIFO.sof
asyn fifo/FIFO.sta.rpt
asyn fifo/FIFO.sta.summary
asyn fifo/FIFO.v
asyn fifo/FIFO.v.bak
asyn fifo/fifo_ctrl.qip
asyn fifo/FIFO_nativelink_simulation.rpt
asyn fifo/greybox_tmp/
asyn fifo/greybox_tmp/cbx_args.txt
asyn fifo/incremental_db/
asyn fifo/incremental_db/compiled_partitions/
asyn fifo/incremental_db/compiled_partitions/FIFO.db_info
asyn fifo/incremental_db/README
asyn fifo/simulation/
asyn fifo/simulation/modelsim/
asyn fifo/simulation/modelsim/FIFO.sft
asyn fifo/simulation/modelsim/FIFO.vo
asyn fifo/simulation/modelsim/FIFO.vt
asyn fifo/simulation/modelsim/FIFO.vt.bak
asyn fifo/simulation/modelsim/FIFO_7_1200mv_0c_slow.vo
asyn fifo/simulation/modelsim/FIFO_7_1200mv_0c_v_slow.sdo
asyn fifo/simulation/modelsim/FIFO_7_1200mv_85c_slow.vo
asyn fifo/simulation/modelsim/FIFO_7_1200mv_85c_v_slow.sdo
asyn fifo/simulation/modelsim/FIFO_min_1200mv_0c_fast.vo
asyn fifo/simulation/modelsim/FIFO_min_1200mv_0c_v_fast.sdo
asyn fifo/simulation/modelsim/FIFO_modelsim.xrf
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak1
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak2
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak3
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak4
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak5
asyn fifo/simulation/modelsim/FIFO_run_msim_rtl_verilog.do.bak6
asyn fifo/simulation/modelsim/FIFO_v.sdo
asyn fifo/simulation/modelsim/msim_transcript
asyn fifo/simulation/modelsim/rtl_work/
asyn fifo/simulation/modelsim/rtl_work/@f@i@f@o/
asyn fifo/simulation/modelsim/rtl_work/@f@i@f@o/verilog.prw
asyn fifo/simulation/modelsim/rtl_work/@f@i@f@o/verilog.psm
asyn fifo/simulation/modelsim/rtl_work/@f@i@f@o/_primary.dat
asyn fifo/simulation/modelsim/rtl_work/@f@i@f@o/_primary.dbs
asyn fifo/simulation/modelsim/rtl_work/@f@i@f@o/_primary.vhd
asyn fifo/simulation/modelsim/rtl_work/_info
asyn fifo/simulation/modelsim/rtl_work/_temp/
asyn fifo/simulation/modelsim/rtl_work/_vmake
asyn fifo/simulation/modelsim/vsim.wlf
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