scmips_cpu/
scmips_cpu/alu.v
scmips_cpu/alu.v.bak
scmips_cpu/alu_test.v
scmips_cpu/alu_test.v.bak
scmips_cpu/cpu.v
scmips_cpu/cpu.v.bak
scmips_cpu/cpu_top.v
scmips_cpu/cpu_top.v.bak
scmips_cpu/cu.v
scmips_cpu/cu.v.bak
scmips_cpu/define.v
scmips_cpu/define.v.bak
scmips_cpu/dff32.v
scmips_cpu/dff32.v.bak
scmips_cpu/mux2x32.v
scmips_cpu/mux2x32.v.bak
scmips_cpu/mux2x5.v
scmips_cpu/mux2x5.v.bak
scmips_cpu/mux4x32.v
scmips_cpu/mux4x32.v.bak
scmips_cpu/ram.v
scmips_cpu/ram.v.bak
scmips_cpu/regfile.v
scmips_cpu/regfile.v.bak
scmips_cpu/rom.v
scmips_cpu/rom.v.bak
scmips_cpu/scmips_cpu.cr.mti
scmips_cpu/scmips_cpu.mpf
scmips_cpu/vsim.wlf
scmips_cpu/work/
scmips_cpu/work/alu/
scmips_cpu/work/alu/verilog.prw
scmips_cpu/work/alu/verilog.psm
scmips_cpu/work/alu/_primary.dat
scmips_cpu/work/alu/_primary.dbs
scmips_cpu/work/alu/_primary.vhd
scmips_cpu/work/alu_test/
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scmips_cpu/work/alu_test/verilog.psm
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scmips_cpu/work/alu_test/_primary.dbs
scmips_cpu/work/alu_test/_primary.vhd
scmips_cpu/work/cpu/
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scmips_cpu/work/cpu/verilog.psm
scmips_cpu/work/cpu/_primary.dat
scmips_cpu/work/cpu/_primary.dbs
scmips_cpu/work/cpu/_primary.vhd
scmips_cpu/work/cpu_top/
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scmips_cpu/work/cpu_top/verilog.psm
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scmips_cpu/work/cu/
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scmips_cpu/work/cu/_primary.dat
scmips_cpu/work/cu/_primary.dbs
scmips_cpu/work/cu/_primary.vhd
scmips_cpu/work/dff/
scmips_cpu/work/dff32/
scmips_cpu/work/dff32/verilog.prw
scmips_cpu/work/dff32/verilog.psm
scmips_cpu/work/dff32/_primary.dat
scmips_cpu/work/dff32/_primary.dbs
scmips_cpu/work/dff32/_primary.vhd
scmips_cpu/work/dff/verilog.prw
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scmips_cpu/work/dff/_primary.dat
scmips_cpu/work/dff/_primary.dbs
scmips_cpu/work/dff/_primary.vhd
scmips_cpu/work/mux2x32/
scmips_cpu/work/mux2x32/verilog.prw
scmips_cpu/work/mux2x32/verilog.psm
scmips_cpu/work/mux2x32/_primary.dat
scmips_cpu/work/mux2x32/_primary.dbs
scmips_cpu/work/mux2x32/_primary.vhd
scmips_cpu/work/mux2x5/
scmips_cpu/work/mux2x5/verilog.prw
scmips_cpu/work/mux2x5/verilog.psm
scmips_cpu/work/mux2x5/_primary.dat
scmips_cpu/work/mux2x5/_primary.dbs
scmips_cpu/work/mux2x5/_primary.vhd
scmips_cpu/work/mux4x32/
scmips_cpu/work/mux4x32/verilog.prw
scmips_cpu/work/mux4x32/verilog.psm
scmips_cpu/work/mux4x32/_primary.dat
scmips_cpu/work/mux4x32/_primary.dbs
scmips_cpu/work/mux4x32/_primary.vhd
scmips_cpu/work/ram/
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scmips_cpu/work/ram/_primary.dat
scmips_cpu/work/ram/_primary.dbs
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scmips_cpu/work/regfile/
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scmips_cpu/work/regfile/_primary.dat
scmips_cpu/work/regfile/_primary.dbs
scmips_cpu/work/regfile/_primary.vhd
scmips_cpu/work/rom/
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scmips_cpu/work/rom/verilog.psm
scmips_cpu/work/rom/_primary.dat
scmips_cpu/work/rom/_primary.dbs
scmips_cpu/work/rom/_primary.vhd
scmips_cpu/work/_info
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scmips_cpu/work/_vmake
scmips_cpu/日志文档.doc