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文件名称:AT510-BU-98000-r0p0-00rel0

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2014-05-02
  • 文件大小：
    1.17mb
  • 已下载：
    6次
  • 提 供 者：
    z****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

CORTEX-M0处理器官方公开的源代码包！采用模糊网表生成，不可读但可综合可仿真可流片，还有testbench示例，很宝贵的资料！-CORTEX-M0 processor officially open source code package! Netlist generated by fuzzy, unreadable but comprehensive simulation can be taped, as well as testbench example, very valuable information!
(系统自动生成,下载前可以参看下载内容)

下载文件列表

AT510-BU-98000-r0p0-00rel0/ARM_Cortex-M0_DesignStart_ReleaseNote.pdf
AT510-BU-98000-r0p0-00rel0/AT510-BU-98000-r0p0-00rel0.lst
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/cortexm0ds_tb.v
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/helloworld.c
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/.ncv.lock
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/cds.lib
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/hdl.var
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/.ncrun.lock
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/.ncv.lock
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/bind.lst.lnx86
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/cds.lib
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/cdsrun.lib
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/files.ts
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/hdl.var
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/hdlrun.var
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/ncelab.args
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/ncelab.env
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/ncsim.args
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/ncsim.env
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/ncsim_restart.args
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/ncsim_restart.env
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/ncverilog.args
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/ncvlog.args
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/ncvlog.env
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/ncvlog.files
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/ncvlog.hrd
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/.ncrun.lock
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/.ncv.lock
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/bind.lst.lnx86
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/cds.lib
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/cdsrun.lib
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/files.ts
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/hdl.var
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/hdlrun.var
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/ncelab.args
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/ncelab.env
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/ncsim.args
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/ncsim.env
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/ncsim_restart.args
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/ncsim_restart.env
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/ncverilog.args
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/ncvlog.args
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/ncvlog.env
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/ncvlog.files
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/ncvlog.hrd
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/verilog/.cdsvmod
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/verilog/.inca.db.169.lnx86
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/verilog/cdsinfo.tag
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/verilog/inca.lnx86.169.pak
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/worklib/.cdsvmod
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/worklib/.inca.db.169.lnx86
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/worklib/cdsinfo.tag
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/worklib/inca.lnx86.169.pak
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/Makefile
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/ncverilog.key
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/ncverilog.log
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/ram.bin
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/verilog/CORTEXM0DS.v
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/verilog/cortexm0ds_logic.v
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/irun.lnx86.08.20.nc/temp
AT510-BU-98000-r0p0-00rel0/logical/cortexm0ds/tbench/INCA_libs/snap.nc/temp
AT510-BU-98000-r

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