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文件名称:Digital_Logic_Design_FPGA

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2014-05-04
  • 文件大小：
    624.76kb
  • 已下载：
    0次
  • 提 供 者：
    李***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

用verilog语言编写的程序，哈工大电子信息工程专业FPGA课程编写程序-



Using verilog language program, HIT Electronic and Information Engineering FPGA programming courses
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Digital_Logic_Design/Lab15_sw2reg/.prj
Digital_Logic_Design/Lab15_sw2reg/.stx
Digital_Logic_Design/Lab15_sw2reg/.xst
Digital_Logic_Design/Lab15_sw2reg/clkdiv.v
Digital_Logic_Design/Lab15_sw2reg/clock_pulse.v
Digital_Logic_Design/Lab15_sw2reg/iseconfig/sw2reg.projectmgr
Digital_Logic_Design/Lab15_sw2reg/iseconfig/sw2regtop.xreport
Digital_Logic_Design/Lab15_sw2reg/iseconfig/sw2reg_top.xreport
Digital_Logic_Design/Lab15_sw2reg/par_usage_statistics.html
Digital_Logic_Design/Lab15_sw2reg/register.v
Digital_Logic_Design/Lab15_sw2reg/se2regtop.ucf
Digital_Logic_Design/Lab15_sw2reg/sw2reg.gise
Digital_Logic_Design/Lab15_sw2reg/sw2reg.xise
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.bgn
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.bit
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.bld
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.cmd_log
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.drc
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.lso
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.ncd
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.ngc
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.ngd
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.ngr
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.pad
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.par
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.pcf
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.prj
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.ptwx
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.stx
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.syr
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.twr
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.twx
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.unroutes
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.ut
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.v
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.xpi
Digital_Logic_Design/Lab15_sw2reg/sw2regtop.xst
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_bitgen.xwbt
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_envsettings.html
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_guide.ncd
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_map.map
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_map.mrp
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_map.ncd
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_map.ngm
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_map.xrpt
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_ngdbuild.xrpt
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_pad.csv
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_pad.txt
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_par.xrpt
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_summary.html
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_summary.xml
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_usage.xml
Digital_Logic_Design/Lab15_sw2reg/sw2regtop_xst.xrpt
Digital_Logic_Design/Lab15_sw2reg/sw2reg_top.cmd_log
Digital_Logic_Design/Lab15_sw2reg/sw2reg_top.lso
Digital_Logic_Design/Lab15_sw2reg/sw2reg_top.prj
Digital_Logic_Design/Lab15_sw2reg/sw2reg_top.syr
Digital_Logic_Design/Lab15_sw2reg/sw2reg_top.v
Digital_Logic_Design/Lab15_sw2reg/sw2reg_top.xst
Digital_Logic_Design/Lab15_sw2reg/sw2reg_top_envsettings.html
Digital_Logic_Design/Lab15_sw2reg/sw2reg_top_summary.html
Digital_Logic_Design/Lab15_sw2reg/sw2reg_top_xst.xrpt
Digital_Logic_Design/Lab15_sw2reg/usage_statistics_webtalk.html
Digital_Logic_Design/Lab15_sw2reg/webtalk.log
Digital_Logic_Design/Lab15_sw2reg/webtalk_pn.xml
Digital_Logic_Design/Lab15_sw2reg/x7segbc.lso
Digital_Logic_Design/Lab15_sw2reg/x7segbc.prj
Digital_Logic_Design/Lab15_sw2reg/x7segbc.stx
Digital_Logic_Design/Lab15_sw2reg/x7segbc.v
Digital_Logic_Design/Lab15_sw2reg/x7segbc.xst
Digital_Logic_Design/Lab15_sw2reg/xlnx_auto_0_xdb/cst.xbcd
Digital_Logic_Design/Lab15_sw2reg/xst/work/work.sdbl
Digital_Logic_Design/Lab15_sw2reg/xst/work/work.sdbx
Digital_Logic_Design/Lab15_sw2reg/_ngo/netlist.lst
Digital_Logic_Design/Lab15_sw2reg/_xmsgs/bitgen.xmsgs
Digital_Logic_Design/Lab15_sw2reg/_xmsgs/map.xmsgs
Digital_Logic_Design/Lab15_sw2reg/_xmsgs/ngdbuild.xmsgs
Digital_Logic_Design/Lab15_sw2reg/_xmsgs/par.xmsgs
Digital_Logic_Design/Lab15_sw2reg/_xmsgs/pn_parser.xmsgs
Digital_Logic_Design/Lab15_sw2reg/_xmsgs/trce.xmsgs
Digital_Logic_Design/Lab15_sw2reg/_xmsgs/xst.xmsgs
Digital_Logic_Design/Lab1_gate2/fuse.log
Digital_Logic_Design/Lab1_gate2/fuse.xmsgs
Digital_Logic_Design/Lab1_gate2/fuseRelaunch.cmd
Digital_Logic_Design/Lab1_gate2/gate2.gise
Digital_Logic_Design/Lab1_gate2/gate2.xise
Digital_Logic_Design/Lab1_gate2/gates2.bgn
Digital_Logic_Design/Lab1_gate2/gates2.bit
Digital_Logic_Design/Lab1_gate2/gates2.bld
Digital_Logic_Design/Lab1_gate2/gates2.cmd_log
Digital_Logic_Design/Lab1_gate2/gates2.drc
Digital_Logic_Design/Lab1_gate2/gates2.lso
Digital_Logic_Design/Lab1_gate2/gates2.ncd
Digital_Logic_Design/Lab1_gate2/gates2.ngc
Digital_Logic_Design/Lab1_gate2/gates2.ngd
Digital_Logic_Design/Lab1_gate2/gates2.ngr
Digital_Logic_Design/Lab1_gate2/gates2.pad
Digital_Logic_Design/Lab1_gate2/gates2.par
Digital_Logic_Design/Lab1_gate2/gates2.pcf
Digital_Logic_Design/Lab1_gate2/gates2.prj
Digital_Logic_Design/Lab1_gate2/gates2.ptwx
Digital_Logic_Design/Lab1_gate2/gates2.stx
Digital_Logic_Design/Lab1_gate2/gates2.syr
Digital_Logic_Design/Lab1_gate2/gates2.twr
Digital_Log

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