文件名称:1Assignment
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Good PCB layout techniques require understanding of non-zero trace impedance effects and coupling of signals, from one circuit to another through parasitic capacitances. SI analysis is essential for any board design, which ensures the proper functioning of the board.
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下载文件列表
文件名 | 大小 | 更新时间 |
---|---|---|
1Assignment/allegro/1N4007.txt | ||
1Assignment/allegro/78XXSIP1.txt | ||
1Assignment/allegro/78XXSIP2.txt | ||
1Assignment/allegro/allegro.jrl | ||
1Assignment/allegro/allegro.jrl | 1 | |
1Assignment/allegro/AT89C51_5.txt | ||
1Assignment/allegro/BC548.txt | ||
1Assignment/allegro/CAPSM.txt | ||
1Assignment/allegro/CAP_NP.txt | ||
1Assignment/allegro/CON2.txt | ||
1Assignment/allegro/CRYSTAL.txt | ||
1Assignment/allegro/devices.dml | ||
1Assignment/allegro/devices.dml | 1 | |
1Assignment/allegro/devices.map | ||
1Assignment/allegro/ibis_models.inc | 1 | |
1Assignment/allegro/interconn.iml | ||
1Assignment/allegro/interconn.iml | 1 | |
1Assignment/allegro/L293D_1.txt | ||
1Assignment/allegro/LCDMODULE16X2.txt | ||
1Assignment/allegro/LED.txt | ||
1Assignment/allegro/master.tag | ||
1Assignment/allegro/MOTOR_AC.txt | ||
1Assignment/allegro/N04325 | ||
1Assignment/allegro/N04398 | ||
1Assignment/allegro/N45629 | ||
1Assignment/allegro/N71837 | ||
1Assignment/allegro/N72058 | ||
1Assignment/allegro/N72058.top | ||
1Assignment/allegro/NE555_0.txt | ||
1Assignment/allegro/netin.log | ||
1Assignment/allegro/NOT_1.txt | ||
1Assignment/allegro/NOT_2.txt | ||
1Assignment/allegro/NOT_3.txt | ||
1Assignment/allegro/NOT_4.txt | ||
1Assignment/allegro/NOT_5.txt | ||
1Assignment/allegro/NOT_6.txt | ||
1Assignment/allegro/POT.txt | ||
1Assignment/allegro/RELAY_DPDT_0.txt | ||
1Assignment/allegro/RELAY_SPDT_0.txt | ||
1Assignment/allegro/RESISTOR.txt | ||
1Assignment/allegro/RIT_ASST-1.brd | ||
1Assignment/allegro/RIT_ASST-1.log | ||
1Assignment/allegro/RIT_ASST-1.txt | ||
1Assignment/allegro/RIT_ASST-6.brd | ||
1Assignment/allegro/RIT_ASST-6.log | ||
1Assignment/allegro/RIT_ASST-6.txt | ||
1Assignment/allegro/RIT_ASST-7.brd | ||
1Assignment/allegro/RIT_ASST-7.log | ||
1Assignment/allegro/RIT_ASST-7.txt | ||
1Assignment/allegro/RIT_ASST-9.brd | ||
1Assignment/allegro/signoise.log | ||
1Assignment/allegro/signoise.log | 1 | |
1Assignment/allegro/signoise.log | 2 | |
1Assignment/allegro/signoise.log | 3 | |
1Assignment/allegro/signoise.run/case1/case.cfg | ||
1Assignment/allegro/signoise.run/case1/case.cfg | 1 | |
1Assignment/allegro/signoise.run/cases.cfg | ||
1Assignment/allegro/signoise.run/cases.cfg | 1 | |
1Assignment/allegro/signoise.run/signoise.cfg | ||
1Assignment/allegro/signoise.run/signoise.cfg | 1 | |
1Assignment/allegro/sigwave.jrl | ||
1Assignment/allegro/sigwave.jrl | 1 | |
1Assignment/allegro/sigxp.dml | ||
1Assignment/allegro/sigxp.dml | 1 | |
1Assignment/allegro/sigxp.jrl | ||
1Assignment/allegro/sigxp.jrl | 1 | |
1Assignment/allegro/sigxp.run/case0/case.cfg | ||
1Assignment/allegro/sigxp.run/case0/case.cfg | 1 | |
1Assignment/allegro/sigxp.run/case0/projstate.dat | ||
1Assignment/allegro/sigxp.run/case0/projstate.dat | 1 | |
1Assignment/allegro/sigxp.run/case0/sigsimcntl.dat | ||
1Assignment/allegro/sigxp.run/case0/sigsimres.dat | ||
1Assignment/allegro/sigxp.run/case0/sim1/comps.spc | ||
1Assignment/allegro/sigxp.run/case0/sim1/comp_rlgc.inc | ||
1Assignment/allegro/sigxp.run/case0/sim1/cycle.msm | ||
1Assignment/allegro/sigxp.run/case0/sim1/cycle.msm | 1 | |
1Assignment/allegro/sigxp.run/case0/sim1/delay.dl | ||
1Assignment/allegro/sigxp.run/case0/sim1/delay.dl | 1 | |
1Assignment/allegro/sigxp.run/case0/sim1/distortion.dst | ||
1Assignment/allegro/sigxp.run/case0/sim1/distortion.dst | 1 | |
1Assignment/allegro/sigxp.run/case0/sim1/ibis_models.inc | ||
1Assignment/allegro/sigxp.run/case0/sim1/interconn.spc | ||
1Assignment/allegro/sigxp.run/case0/sim1/main.spc | ||
1Assignment/allegro/sigxp.run/case0/sim1/ntl_rlgc.inc | ||
1Assignment/allegro/sigxp.run/case0/sim1/stimulus.spc | ||
1Assignment/allegro/sigxp.run/case0/sim1/tlsim.log | ||
1Assignment/allegro/sigxp.run/case0/sim1/tlsim.log | 1 | |
1Assignment/allegro/sigxp.run/case0/sim1/tlsim.log | 2 | |
1Assignment/allegro/sigxp.run/case0/sim1/tlsim.log | 3 | |
1Assignment/allegro/sigxp.run/case0/sim2/comps.spc | ||
1Assignment/allegro/sigxp.run/case0/sim2/comp_rlgc.inc | ||
1Assignment/allegro/sigxp.run/case0/sim2/cycle.msm | ||
1Assignment/allegro/sigxp.run/case0/sim2/cycle.msm | 1 | |
1Assignment/allegro/sigxp.run/case0/sim2/delay.dl | ||
1Assignment/allegro/sigxp.run/case0/sim2/delay.dl | 1 | |
1Assignment/allegro/sigxp.run/case0/sim2/distortion.dst | ||
1Assignment/allegro/sigxp.run/case0/sim2/distortion.dst | 1 | |
1Assignment/allegro/sigxp.run/case0/sim2/ibis_models.inc | ||
1Assignment/allegro/sigxp.run/case0/sim2/interconn.spc | ||
1Assignment/allegro/sigxp.run/case0/sim2/main.spc | ||
1Assignment/allegro/sigxp.run/case0/sim2/ntl_rlgc.inc | ||
1Assignment/allegro/sigxp.run/case0/sim2/stimulus.spc | ||
1Assignment/allegro/sigxp.run/case0/sim2/tlsim.log | ||
1Assignment/allegro/sigxp.run/case0/sim2/tlsim.log | 1 | |
1Assignment/allegro/sigxp.run/case0/sim2/tlsim.log | 2 | |
1Assignment/allegro/sigxp.run/case0/waveforms/sim1.cim | ||
1Assignment/allegro/sigxp.run/case0/waveforms/sim1.sim | ||
1Assignment/allegro/sigxp.run/case0/waveforms/sim1_emi.sim | ||
1Assignment/allegro/sigxp.run/case0/waveforms/sim1_emi_db.sim | ||
1Assignment/allegro/sigxp.run/case0/waveforms/sim2.cim | ||
1Assignment/allegro/sigxp.run/case0/waveforms/sim2.sim | ||
1Assignment/allegro/sigxp.run/case0/waveforms/sim2_emi.sim | ||
1Assignment/allegro/sigxp.run/case0/waveforms/sim2_emi_db.sim | ||
1Assignment/allegro/sigxp.run/cases.cfg | ||
1Assignment/allegro/sigxp.run/cases.cfg | 1 | |
1Assignment/allegro/sigxp.run/signoise.cfg | ||
1Assignment/allegro/sigxp.run/signoise.cfg | 1 | |
1Assignment/allegro/stderror.log | ||
1Assignment/allegro/sweep_rpt_tab.txt | ||
1Assignment/allegro/SW_PUSHBUTTON.txt | ||
1Assignment/Backup0.max | ||
1Assignment/BACKUP1.MAX | ||
1Assignment/BACKUP2.MAX | ||
1Assignment/BACKUP3.MAX | ||
1Assignment |
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