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文件名称:ug480-ver1.5

  • 所属分类：
    Com Port
  • 标签属性：
    [PDF]
  • 上传时间：
    2014-05-07
  • 文件大小：
    6.34mb
  • 已下载：
    0次
  • 提 供 者：
    梅*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

利用实验板上的XADC资源，对芯片温度、内部电源进行定时采集和监控，并把信息存入blockram,可实现翻看，并有按键消抖模块-XADC resource use experimental board, the chip temperature, the internal power supply timing collection and monitoring, and put information into blockram, look can be achieved, and a key debounce module
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ug480-ver1.5/.Xil/PlanAhead-6216-PC201402151702/ngc2edif/ngc2edif.log
ug480-ver1.5/.Xil/PlanAhead-6216-PC201402151702/ngc2edif/_xmsgs/ngc2edif.xmsgs
ug480-ver1.5/.Xil/PlanAhead-6228-PC201402151702/ngc2edif/IP_ram.edif
ug480-ver1.5/AA.v
ug480-ver1.5/AA_isim_beh.exe
ug480-ver1.5/AA_stx_beh.prj
ug480-ver1.5/aw.v
ug480-ver1.5/blockram.v
ug480-ver1.5/blockram_envsettings.html
ug480-ver1.5/blockram_summary.html
ug480-ver1.5/dfsdf.v
ug480-ver1.5/dfsdf_beh.prj
ug480-ver1.5/dfsdf_isim_beh.exe
ug480-ver1.5/dfsdf_isim_beh.wdb
ug480-ver1.5/dfsdf_stx_beh.prj
ug480-ver1.5/fenpin.lso
ug480-ver1.5/fenpin.v
ug480-ver1.5/fuse.log
ug480-ver1.5/fuse.xmsgs
ug480-ver1.5/fuseRelaunch.cmd
ug480-ver1.5/gggg.v
ug480-ver1.5/gggg.vhd
ug480-ver1.5/gggg_beh.prj
ug480-ver1.5/gggg_isim_beh.exe
ug480-ver1.5/gggg_isim_beh.wdb
ug480-ver1.5/gggg_stx_beh.prj
ug480-ver1.5/ipcore_dir/blockram.asy
ug480-ver1.5/ipcore_dir/blockram.gise
ug480-ver1.5/ipcore_dir/blockram.sym
ug480-ver1.5/ipcore_dir/blockram.veo
ug480-ver1.5/ipcore_dir/blockram.xise
ug480-ver1.5/ipcore_dir/blockram_xmdf.tcl
ug480-ver1.5/ipcore_dir/check_versions.tcl
ug480-ver1.5/ipcore_dir/coregen.cgp
ug480-ver1.5/ipcore_dir/coregen.log
ug480-ver1.5/ipcore_dir/core_resources.txt
ug480-ver1.5/ipcore_dir/create_blockram.tcl
ug480-ver1.5/ipcore_dir/create_Dualram.tcl
ug480-ver1.5/ipcore_dir/create_IP_bram.tcl
ug480-ver1.5/ipcore_dir/create_IP_div.tcl
ug480-ver1.5/ipcore_dir/create_IP_inst.tcl
ug480-ver1.5/ipcore_dir/create_IP_mul.tcl
ug480-ver1.5/ipcore_dir/create_IP_multiply.tcl
ug480-ver1.5/ipcore_dir/create_IP_ram.tcl
ug480-ver1.5/ipcore_dir/create_IP_xadc.tcl
ug480-ver1.5/ipcore_dir/create_xadc.tcl
ug480-ver1.5/ipcore_dir/Dualram.asy
ug480-ver1.5/ipcore_dir/Dualram.gise
ug480-ver1.5/ipcore_dir/dualram.ncf
ug480-ver1.5/ipcore_dir/Dualram.sym
ug480-ver1.5/ipcore_dir/Dualram.veo
ug480-ver1.5/ipcore_dir/Dualram.xise
ug480-ver1.5/ipcore_dir/Dualram_xmdf.tcl
ug480-ver1.5/ipcore_dir/edit_blockram.tcl
ug480-ver1.5/ipcore_dir/edit_Dualram.tcl
ug480-ver1.5/ipcore_dir/edit_IP_inst.tcl
ug480-ver1.5/ipcore_dir/edit_IP_mul.tcl
ug480-ver1.5/ipcore_dir/edit_IP_multiply.tcl
ug480-ver1.5/ipcore_dir/edit_IP_ram.tcl
ug480-ver1.5/ipcore_dir/edit_IP_xadc.tcl
ug480-ver1.5/ipcore_dir/gui_latency.txt
ug480-ver1.5/ipcore_dir/IP_bram/blk_mem_gen_v7_3_readme.txt
ug480-ver1.5/ipcore_dir/IP_bram/doc/blk_mem_gen_v7_3_vinfo.html
ug480-ver1.5/ipcore_dir/IP_bram/doc/pg058-blk-mem-gen.pdf
ug480-ver1.5/ipcore_dir/IP_bram/example_design/IP_bram_exdes.ucf
ug480-ver1.5/ipcore_dir/IP_bram/example_design/IP_bram_exdes.vhd
ug480-ver1.5/ipcore_dir/IP_bram/example_design/IP_bram_exdes.xdc
ug480-ver1.5/ipcore_dir/IP_bram/example_design/IP_bram_prod.vhd
ug480-ver1.5/ipcore_dir/IP_bram/implement/implement.bat
ug480-ver1.5/ipcore_dir/IP_bram/implement/implement.sh
ug480-ver1.5/ipcore_dir/IP_bram/implement/planAhead_ise.bat
ug480-ver1.5/ipcore_dir/IP_bram/implement/planAhead_ise.sh
ug480-ver1.5/ipcore_dir/IP_bram/implement/planAhead_ise.tcl
ug480-ver1.5/ipcore_dir/IP_bram/implement/xst.prj
ug480-ver1.5/ipcore_dir/IP_bram/implement/xst.scr
ug480-ver1.5/ipcore_dir/IP_bram/simulation/addr_gen.vhd
ug480-ver1.5/ipcore_dir/IP_bram/simulation/bmg_stim_gen.vhd
ug480-ver1.5/ipcore_dir/IP_bram/simulation/bmg_tb_pkg.vhd
ug480-ver1.5/ipcore_dir/IP_bram/simulation/checker.vhd
ug480-ver1.5/ipcore_dir/IP_bram/simulation/data_gen.vhd
ug480-ver1.5/ipcore_dir/IP_bram/simulation/functional/simcmds.tcl
ug480-ver1.5/ipcore_dir/IP_bram/simulation/functional/simulate_isim.bat
ug480-ver1.5/ipcore_dir/IP_bram/simulation/functional/simulate_mti.bat
ug480-ver1.5/ipcore_dir/IP_bram/simulation/functional/simulate_mti.do
ug480-ver1.5/ipcore_dir/IP_bram/simulation/functional/simulate_mti.sh
ug480-ver1.5/ipcore_dir/IP_bram/simulation/functional/simulate_ncsim.sh
ug480-ver1.5/ipcore_dir/IP_bram/simulation/functional/simulate_vcs.sh
ug480-ver1.5/ipcore_dir/IP_bram/simulation/functional/ucli_commands.key
ug480-ver1.5/ipcore_dir/IP_bram/simulation/functional/vcs_session.tcl
ug480-ver1.5/ipcore_dir/IP_bram/simulation/functional/wave_mti.do
ug480-ver1.5/ipcore_dir/IP_bram/simulation/functional/wave_ncsim.sv
ug480-ver1.5/ipcore_dir/IP_bram/simulation/IP_bram_synth.vhd
ug480-ver1.5/ipcore_dir/IP_bram/simulation/IP_bram_tb.vhd
ug480-ver1.5/ipcore_dir/IP_bram/simulation/random.vhd
ug480-ver1.5/ipcore_dir/IP_bram/simulation/timing/simcmds.tcl
ug480-ver1.5/ipcore_dir/IP_bram/simulation/timing/simulate_isim.bat
ug480-ver1.5/ipcore_dir/IP_bram/simulation/timing/simulate_mti.bat
ug480-ver1.5/ipcore_dir/IP_bram/simulation/timing/simulate_mti.do
ug480-ver1.5/ipcore_dir/IP_bram/simulation/timing/simulate_mti.sh
ug480-ver1.5/ipcore_dir/IP_bram/simulation/timing/simulate_ncsim.sh
ug480-ver1.5/ipcore_dir/IP_bram/simulation/timing/simulate_vcs.sh
ug480-ver1.5/ipcore_dir/IP_bram/simulation/timing/ucli_commands.key
ug480-ver1.5/ipcore_dir/IP_bram/simulation/timing/vcs_session.tcl
ug480-ver1.5/ipcore_dir/IP_bram/simulation/timing/wave_mti.do
ug480-ver1.5/ipcore_dir/IP_bram/simulation/timing/wave_ncsim.sv
ug480-ver1.5/ipcore_dir/IP_bram.asy
ug480-ver1.5/ipcore_dir/IP_bram.gise
ug480-ver1.5/ipcore_dir/IP_br

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