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文件名称:monitoringV5

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  • 上传时间:
    2014-05-07
  • 文件大小:
    5.84mb
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    0次
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介绍说明--下载内容来自于网络,使用问题请自行百度

文件的FPGA是基于Xilinx ISE写的,所用开发板为zedboard7020 484系列,完成的功能为:读取XADC里的温度,VCC,并存储到RAM中,通过流水灯实现翻看,读取等功能.-Document is based on Xilinx ISE FPGA wrote, the use of development board for zedboard7020 484 series, completed functions: reading XADC in temperature, VCC, and stored in the RAM, achieved through water lights look, reading and other functions.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

monitoringV5/
monitoringV5/BlockRAM.prj
monitoringV5/BlockRAM.stx
monitoringV5/BlockRAM.v
monitoringV5/BlockRAM.xst
monitoringV5/BLOCKtest.v
monitoringV5/BLOCKtest_beh.prj
monitoringV5/BLOCKtest_isim_beh.exe
monitoringV5/BLOCKtest_isim_beh.wdb
monitoringV5/BLOCKtest_stx_beh.prj
monitoringV5/block_ram.bgn
monitoringV5/block_ram.bit
monitoringV5/Block_RAM.bld
monitoringV5/Block_RAM.cmd_log
monitoringV5/block_ram.drc
monitoringV5/Block_RAM.lso
monitoringV5/Block_RAM.ncd
monitoringV5/Block_RAM.ngc
monitoringV5/Block_RAM.ngd
monitoringV5/Block_RAM.ngr
monitoringV5/Block_RAM.pad
monitoringV5/Block_RAM.par
monitoringV5/Block_RAM.pcf
monitoringV5/Block_RAM.prj
monitoringV5/Block_RAM.ptwx
monitoringV5/Block_RAM.stx
monitoringV5/Block_RAM.syr
monitoringV5/Block_RAM.twr
monitoringV5/Block_RAM.twx
monitoringV5/Block_RAM.ucf
monitoringV5/Block_RAM.unroutes
monitoringV5/Block_RAM.ut
monitoringV5/Block_RAM.xpi
monitoringV5/Block_RAM.xst
monitoringV5/Block_RAM_bitgen.xwbt
monitoringV5/Block_RAM_envsettings.html
monitoringV5/Block_RAM_guide.ncd
monitoringV5/Block_RAM_map.map
monitoringV5/Block_RAM_map.mrp
monitoringV5/Block_RAM_map.ncd
monitoringV5/Block_RAM_map.ngm
monitoringV5/Block_RAM_map.xrpt
monitoringV5/Block_RAM_ngdbuild.xrpt
monitoringV5/Block_RAM_pad.csv
monitoringV5/Block_RAM_pad.txt
monitoringV5/Block_RAM_par.xrpt
monitoringV5/Block_RAM_stx_beh.prj
monitoringV5/Block_RAM_summary.html
monitoringV5/Block_RAM_summary.xml
monitoringV5/Block_RAM_usage.xml
monitoringV5/Block_RAM_xst.xrpt
monitoringV5/fangdou.v
monitoringV5/fuse.log
monitoringV5/ipcore_dir/
monitoringV5/ipcore_dir/BlockRAM/
monitoringV5/ipcore_dir/BlockRAM.asy
monitoringV5/ipcore_dir/BlockRAM.gise
monitoringV5/ipcore_dir/BlockRAM.ncf
monitoringV5/ipcore_dir/BlockRAM.ngc
monitoringV5/ipcore_dir/BlockRAM.sym
monitoringV5/ipcore_dir/BlockRAM.v
monitoringV5/ipcore_dir/BlockRAM.veo
monitoringV5/ipcore_dir/BlockRAM.xco
monitoringV5/ipcore_dir/BlockRAM.xise
monitoringV5/ipcore_dir/BlockRAM/blk_mem_gen_v7_3_readme.txt
monitoringV5/ipcore_dir/BlockRAM/doc/
monitoringV5/ipcore_dir/BlockRAM/doc/blk_mem_gen_v7_3_vinfo.html
monitoringV5/ipcore_dir/BlockRAM/doc/pg058-blk-mem-gen.pdf
monitoringV5/ipcore_dir/BlockRAM/example_design/
monitoringV5/ipcore_dir/BlockRAM/example_design/BlockRAM_exdes.ucf
monitoringV5/ipcore_dir/BlockRAM/example_design/BlockRAM_exdes.vhd
monitoringV5/ipcore_dir/BlockRAM/example_design/BlockRAM_exdes.xdc
monitoringV5/ipcore_dir/BlockRAM/example_design/BlockRAM_prod.vhd
monitoringV5/ipcore_dir/BlockRAM/implement/
monitoringV5/ipcore_dir/BlockRAM/implement/implement.bat
monitoringV5/ipcore_dir/BlockRAM/implement/implement.sh
monitoringV5/ipcore_dir/BlockRAM/implement/planAhead_ise.bat
monitoringV5/ipcore_dir/BlockRAM/implement/planAhead_ise.sh
monitoringV5/ipcore_dir/BlockRAM/implement/planAhead_ise.tcl
monitoringV5/ipcore_dir/BlockRAM/implement/xst.prj
monitoringV5/ipcore_dir/BlockRAM/implement/xst.scr
monitoringV5/ipcore_dir/BlockRAM/simulation/
monitoringV5/ipcore_dir/BlockRAM/simulation/addr_gen.vhd
monitoringV5/ipcore_dir/BlockRAM/simulation/BlockRAM_synth.vhd
monitoringV5/ipcore_dir/BlockRAM/simulation/BlockRAM_tb.vhd
monitoringV5/ipcore_dir/BlockRAM/simulation/bmg_stim_gen.vhd
monitoringV5/ipcore_dir/BlockRAM/simulation/bmg_tb_pkg.vhd
monitoringV5/ipcore_dir/BlockRAM/simulation/checker.vhd
monitoringV5/ipcore_dir/BlockRAM/simulation/data_gen.vhd
monitoringV5/ipcore_dir/BlockRAM/simulation/functional/
monitoringV5/ipcore_dir/BlockRAM/simulation/functional/simcmds.tcl
monitoringV5/ipcore_dir/BlockRAM/simulation/functional/simulate_isim.bat
monitoringV5/ipcore_dir/BlockRAM/simulation/functional/simulate_mti.bat
monitoringV5/ipcore_dir/BlockRAM/simulation/functional/simulate_mti.do
monitoringV5/ipcore_dir/BlockRAM/simulation/functional/simulate_mti.sh
monitoringV5/ipcore_dir/BlockRAM/simulation/functional/simulate_ncsim.sh
monitoringV5/ipcore_dir/BlockRAM/simulation/functional/simulate_vcs.sh
monitoringV5/ipcore_dir/BlockRAM/simulation/functional/ucli_commands.key
monitoringV5/ipcore_dir/BlockRAM/simulation/functional/vcs_session.tcl
monitoringV5/ipcore_dir/BlockRAM/simulation/functional/wave_mti.do
monitoringV5/ipcore_dir/BlockRAM/simulation/functional/wave_ncsim.sv
monitoringV5/ipcore_dir/BlockRAM/simulation/random.vhd
monitoringV5/ipcore_dir/BlockRAM/simulation/timing/
monitoringV5/ipcore_dir/BlockRAM/simulation/timing/simcmds.tcl
monitoringV5/ipcore_dir/BlockRAM/simulation/timing/simulate_isim.bat
monitoringV5/ipcore_dir/BlockRAM/simulation/timing/simulate_mti.bat
monitoringV5/ipcore_dir/BlockRAM/simulation/timing/simulate_mti.do
monitoringV5/ipcore_dir/BlockRAM/simulation/timing/simulate_mti.sh
monitoringV5/ipcore_dir/BlockRAM/simulation/timing/simulate_ncsim.sh
monitoringV5/ipcore_dir/BlockRAM/simulation/timing/simulate_vcs.sh
monitoringV5/ipcore_dir/BlockRAM/simulation/timing/ucli_commands.key
monitoringV5/ipcore_dir/BlockRAM/simulation/timing/vcs_session.tcl
monitoringV5/ipcore_dir/BlockRAM/simulation/timing/wave_mti.do
monitoringV5/ipcore_dir/BlockRAM/simulation/timing/wave_ncsim.sv
monitoringV5/ipcore_dir/BlockRAM_flist.txt
monitoringV5/ipcore_dir/B

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