文件名称:lab1
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- 上传时间：2014-05-07
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文件大小：26.45kb
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初步掌握ModelSim的使用方法,了解TestBench的编写,Verilog HDL的层次设计方法/参数设置、参数传递方法.-Preliminary master the use of ModelSim understand TestBench preparation, Verilog HDL level design methods/parameters, parameter passing methods.
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下载文件列表
lab1/acc/acc.v
lab1/acc/acc_sim.cr.mti
lab1/acc/acc_sim.mpf
lab1/acc/acc_tb.v
lab1/acc/dffr.v
lab1/acc/full_adder.v
lab1/acc/transcript
lab1/acc/vsim.wlf
lab1/acc/wave.do
lab1/acc/work/acc/verilog.asm
lab1/acc/work/acc/_primary.dat
lab1/acc/work/acc/_primary.vhd
lab1/acc/work/acc_tb/verilog.asm
lab1/acc/work/acc_tb/_primary.dat
lab1/acc/work/acc_tb/_primary.vhd
lab1/acc/work/dffr/verilog.asm
lab1/acc/work/dffr/_primary.dat
lab1/acc/work/dffr/_primary.vhd
lab1/acc/work/full_adder/verilog.asm
lab1/acc/work/full_adder/_primary.dat
lab1/acc/work/full_adder/_primary.vhd
lab1/acc/work/_info
lab1/acc/work/acc
lab1/acc/work/acc_tb
lab1/acc/work/dffr
lab1/acc/work/full_adder
lab1/acc/work
lab1/acc
lab1
lab1/acc/acc_sim.cr.mti
lab1/acc/acc_sim.mpf
lab1/acc/acc_tb.v
lab1/acc/dffr.v
lab1/acc/full_adder.v
lab1/acc/transcript
lab1/acc/vsim.wlf
lab1/acc/wave.do
lab1/acc/work/acc/verilog.asm
lab1/acc/work/acc/_primary.dat
lab1/acc/work/acc/_primary.vhd
lab1/acc/work/acc_tb/verilog.asm
lab1/acc/work/acc_tb/_primary.dat
lab1/acc/work/acc_tb/_primary.vhd
lab1/acc/work/dffr/verilog.asm
lab1/acc/work/dffr/_primary.dat
lab1/acc/work/dffr/_primary.vhd
lab1/acc/work/full_adder/verilog.asm
lab1/acc/work/full_adder/_primary.dat
lab1/acc/work/full_adder/_primary.vhd
lab1/acc/work/_info
lab1/acc/work/acc
lab1/acc/work/acc_tb
lab1/acc/work/dffr
lab1/acc/work/full_adder
lab1/acc/work
lab1/acc
lab1
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