文件名称:lab16
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- 上传时间:2014-05-07
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文件大小:33.4kb
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数字式秒表大实验的设计代码,并附加测试代码-Digital stopwatch big experiment design code and test code attached
(系统自动生成,下载前可以参看下载内容)
下载文件列表
lab16/sim/dff.v
lab16/sim/dff.v.bak
lab16/sim/dffr.v
lab16/sim/dffr.v.bak
lab16/sim/lab_16.cr.mti
lab16/sim/lab_16.mpf
lab16/sim/mkbh.v
lab16/sim/mkbh.v.bak
lab16/sim/synch.v
lab16/sim/synch.v.bak
lab16/sim/work/button_press_unit_tb/verilog.asm
lab16/sim/work/button_press_unit_tb/_primary.dat
lab16/sim/work/button_press_unit_tb/_primary.vhd
lab16/sim/work/control_2_tb_v/verilog.asm
lab16/sim/work/control_2_tb_v/_primary.dat
lab16/sim/work/control_2_tb_v/_primary.vhd
lab16/sim/work/dff/verilog.asm
lab16/sim/work/dff/_primary.dat
lab16/sim/work/dff/_primary.vhd
lab16/sim/work/dffr/verilog.asm
lab16/sim/work/dffr/_primary.dat
lab16/sim/work/dffr/_primary.vhd
lab16/sim/work/stopwatch/verilog.asm
lab16/sim/work/stopwatch/_primary.dat
lab16/sim/work/stopwatch/_primary.vhd
lab16/sim/work/stopwatch_tb_v/verilog.asm
lab16/sim/work/stopwatch_tb_v/_primary.dat
lab16/sim/work/stopwatch_tb_v/_primary.vhd
lab16/sim/work/synch/verilog.asm
lab16/sim/work/synch/_primary.dat
lab16/sim/work/synch/_primary.vhd
lab16/sim/work/_info
lab16/src/button_press_unit_tb.v
lab16/src/control_2_tb.v
lab16/src/stopwatch.ucf
lab16/src/stopwatch.v
lab16/src/stopwatch_tb.v
lab16/sim/work/button_press_unit_tb
lab16/sim/work/control_2_tb_v
lab16/sim/work/dff
lab16/sim/work/dffr
lab16/sim/work/stopwatch
lab16/sim/work/stopwatch_tb_v
lab16/sim/work/synch
lab16/sim/work
lab16/ise
lab16/sim
lab16/src
lab16
lab16/sim/dff.v.bak
lab16/sim/dffr.v
lab16/sim/dffr.v.bak
lab16/sim/lab_16.cr.mti
lab16/sim/lab_16.mpf
lab16/sim/mkbh.v
lab16/sim/mkbh.v.bak
lab16/sim/synch.v
lab16/sim/synch.v.bak
lab16/sim/work/button_press_unit_tb/verilog.asm
lab16/sim/work/button_press_unit_tb/_primary.dat
lab16/sim/work/button_press_unit_tb/_primary.vhd
lab16/sim/work/control_2_tb_v/verilog.asm
lab16/sim/work/control_2_tb_v/_primary.dat
lab16/sim/work/control_2_tb_v/_primary.vhd
lab16/sim/work/dff/verilog.asm
lab16/sim/work/dff/_primary.dat
lab16/sim/work/dff/_primary.vhd
lab16/sim/work/dffr/verilog.asm
lab16/sim/work/dffr/_primary.dat
lab16/sim/work/dffr/_primary.vhd
lab16/sim/work/stopwatch/verilog.asm
lab16/sim/work/stopwatch/_primary.dat
lab16/sim/work/stopwatch/_primary.vhd
lab16/sim/work/stopwatch_tb_v/verilog.asm
lab16/sim/work/stopwatch_tb_v/_primary.dat
lab16/sim/work/stopwatch_tb_v/_primary.vhd
lab16/sim/work/synch/verilog.asm
lab16/sim/work/synch/_primary.dat
lab16/sim/work/synch/_primary.vhd
lab16/sim/work/_info
lab16/src/button_press_unit_tb.v
lab16/src/control_2_tb.v
lab16/src/stopwatch.ucf
lab16/src/stopwatch.v
lab16/src/stopwatch_tb.v
lab16/sim/work/button_press_unit_tb
lab16/sim/work/control_2_tb_v
lab16/sim/work/dff
lab16/sim/work/dffr
lab16/sim/work/stopwatch
lab16/sim/work/stopwatch_tb_v
lab16/sim/work/synch
lab16/sim/work
lab16/ise
lab16/sim
lab16/src
lab16
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