// --- --- --- --- --- --- --- --- --- --- --- --

// Copyright (c) 2007 by Terasic Technologies Inc.

// --------------------------------------------------------------------

//

// Permission:

//

// Terasic grants permission to use and modify this code for use

// in synthesis for all Terasic Development Boards and Altera Development

// Kits made by Terasic. Other use of this code, including the selling

// ,duplication, or modification of any portion is strictly prohibited.

//

// Disclaimer:

//

// This VHDL/Verilog or C/C++ source code is intended as a design reference

// which illustrates how these types of functions can be implemented.

// It is the user s responsibility to verify their design for

// consistency and functionality through the use of formal

// verification methods. Terasic provides no warranty regarding the use

// or functionality of this code.

//

// -// --------------------------------------------------------------------

// Copyright (c) 2007 by Terasic Technologies Inc.

// --------------------------------------------------------------------

//

// Permission:

//

//　 Terasic grants permission to use and modify this code for use

//　 in synthesis for all Terasic Development Boards and Altera Development

//　 Kits made by Terasic.　Other use of this code, including the selling

//　 ,duplication, or modification of any portion is strictly prohibited.

//

// Disclaimer:

//

//　 This VHDL/Verilog or C/C++ source code is intended as a design reference

//　 which illustrates how these types of functions can be implemented.

//　 It is the user s responsibility to verify their design for

//　 consistency and functionality through the use of formal

//　 verification methods.　Terasic provides no warranty regarding the use

//　 or functionality of this code.

//

// --------------------------------------------------------------------