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文件名称:clock_lcd

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2014-05-26
  • 文件大小：
    199.11kb
  • 已下载：
    1次
  • 提 供 者：
    周***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于altera FPGA的多功能数字钟程序，但是不是简单的数字钟，还支持VGA图形化钟表显示，并且有鼠标，键盘，温度显示等等功能。-Altera FPGA based multi-functional digital clock program, but not a simple digital clock, timepiece also supports VGA graphics display, and there is a mouse, keyboard, temperature display and more.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

clock_lcd/alarm.v
clock_lcd/alarm.v.bak
clock_lcd/beep.v
clock_lcd/beep.v.bak
clock_lcd/circle.v
clock_lcd/circle.v.bak
clock_lcd/clock.asm.rpt
clock_lcd/clock.done
clock_lcd/clock.fit.rpt
clock_lcd/clock.fit.smsg
clock_lcd/clock.fit.summary
clock_lcd/clock.flow.rpt
clock_lcd/clock.map.rpt
clock_lcd/clock.map.smsg
clock_lcd/clock.map.summary
clock_lcd/clock.pin
clock_lcd/clock.pof
clock_lcd/clock.qpf
clock_lcd/clock.qsf
clock_lcd/clock.qws
clock_lcd/clock.sof
clock_lcd/clock.tan.rpt
clock_lcd/clock.tan.summary
clock_lcd/clock.v
clock_lcd/clock.v.bak
clock_lcd/clock_assignment_defaults.qdf
clock_lcd/clock_sub.v
clock_lcd/clock_sub.v.bak
clock_lcd/color_to_hex.v
clock_lcd/color_to_hex.v.bak
clock_lcd/counter.v
clock_lcd/counter.v.bak
clock_lcd/db/add_sub_05h.tdf
clock_lcd/db/add_sub_15h.tdf
clock_lcd/db/add_sub_2ch.tdf
clock_lcd/db/add_sub_6ch.tdf
clock_lcd/db/add_sub_lkc.tdf
clock_lcd/db/add_sub_mkc.tdf
clock_lcd/db/add_sub_ufh.tdf
clock_lcd/db/add_sub_vfh.tdf
clock_lcd/db/altsyncram_9qv.tdf
clock_lcd/db/altsyncram_aqv.tdf
clock_lcd/db/altsyncram_bqv.tdf
clock_lcd/db/altsyncram_cqv.tdf
clock_lcd/db/altsyncram_dqv.tdf
clock_lcd/db/altsyncram_m981.tdf
clock_lcd/db/altsyncram_nrv.tdf
clock_lcd/db/altsyncram_o981.tdf
clock_lcd/db/altsyncram_orv.tdf
clock_lcd/db/altsyncram_prv.tdf
clock_lcd/db/altsyncram_q981.tdf
clock_lcd/db/altsyncram_qrv.tdf
clock_lcd/db/altsyncram_rrv.tdf
clock_lcd/db/altsyncram_s0v.tdf
clock_lcd/db/altsyncram_vrv.tdf
clock_lcd/db/alt_u_div_ove.tdf
clock_lcd/db/clock.db_info
clock_lcd/db/clock.sld_design_entry.sci
clock_lcd/db/cmpr_9cc.tdf
clock_lcd/db/cntr_cmf.tdf
clock_lcd/db/cntr_dmf.tdf
clock_lcd/db/logic_util_heursitic.dat
clock_lcd/db/lpm_divide_1dm.tdf
clock_lcd/db/mult_71t.tdf
clock_lcd/db/mult_mat.tdf
clock_lcd/db/mult_tat.tdf
clock_lcd/db/prev_cmp_clock.asm.qmsg
clock_lcd/db/prev_cmp_clock.fit.qmsg
clock_lcd/db/prev_cmp_clock.map.qmsg
clock_lcd/db/prev_cmp_clock.qmsg
clock_lcd/db/prev_cmp_clock.tan.qmsg
clock_lcd/db/shift_taps_9jm.tdf
clock_lcd/db/shift_taps_ajm.tdf
clock_lcd/db/shift_taps_bjm.tdf
clock_lcd/db/sign_div_unsign_bkh.tdf
clock_lcd/incremental_db/compiled_partitions/clock.db_info
clock_lcd/incremental_db/compiled_partitions/clock.root_partition.cmp.dfp
clock_lcd/incremental_db/compiled_partitions/clock.root_partition.cmp.kpt
clock_lcd/incremental_db/compiled_partitions/clock.root_partition.cmp.logdb
clock_lcd/incremental_db/compiled_partitions/clock.root_partition.map.dpi
clock_lcd/incremental_db/compiled_partitions/clock.root_partition.map.kpt
clock_lcd/incremental_db/README
clock_lcd/key.v
clock_lcd/key.v.bak
clock_lcd/lcd.v
clock_lcd/lcd.v.bak
clock_lcd/mouse.v
clock_lcd/mouse.v.bak
clock_lcd/ps2_key.v
clock_lcd/ps2_key.v.bak
clock_lcd/ps2_mouse_ctr.v
clock_lcd/ps2_to_hex.v
clock_lcd/ps2_to_hex.v.bak
clock_lcd/regshow.v
clock_lcd/regshow.v.bak
clock_lcd/tempe.v
clock_lcd/tempe.v.bak
clock_lcd/uart.v
clock_lcd/uart.v.bak
clock_lcd/uart_r.v
clock_lcd/uart_r.v.bak
clock_lcd/uart_r2.v
clock_lcd/uart_r2.v.bak
clock_lcd/uart_r3.v
clock_lcd/uart_r3.v.bak
clock_lcd/uart_r4.v
clock_lcd/uart_r4.v.bak
clock_lcd/uart_t.v
clock_lcd/uart_t.v.bak
clock_lcd/uart_t3.v
clock_lcd/uart_t3.v.bak
clock_lcd/vga.v
clock_lcd/vga.v.bak
clock_lcd/vga_digital.v
clock_lcd/vga_digital.v.bak
clock_lcd/incremental_db/compiled_partitions
clock_lcd/db
clock_lcd/incremental_db
clock_lcd

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