spi/
spi/CVS/
spi/CVS/Root
spi/CVS/Repository
spi/CVS/Entries
spi/bench/
spi/bench/CVS/
spi/bench/CVS/Root
spi/bench/CVS/Repository
spi/bench/CVS/Entries
spi/bench/verilog/
spi/bench/verilog/CVS/
spi/bench/verilog/CVS/Root
spi/bench/verilog/CVS/Repository
spi/bench/verilog/CVS/Entries
spi/bench/verilog/spi_slave_model.v
spi/bench/verilog/tb_spi_top.v
spi/bench/verilog/wb_master_model.v
spi/doc/
spi/doc/CVS/
spi/doc/CVS/Root
spi/doc/CVS/Repository
spi/doc/CVS/Entries
spi/doc/spi.pdf
spi/doc/src/
spi/doc/src/CVS/
spi/doc/src/CVS/Root
spi/doc/src/CVS/Repository
spi/doc/src/CVS/Entries
spi/doc/src/spi.doc
spi/rtl/
spi/rtl/CVS/
spi/rtl/CVS/Root
spi/rtl/CVS/Repository
spi/rtl/CVS/Entries
spi/rtl/verilog/
spi/rtl/verilog/CVS/
spi/rtl/verilog/CVS/Root
spi/rtl/verilog/CVS/Repository
spi/rtl/verilog/CVS/Entries
spi/rtl/verilog/spi_clgen.v
spi/rtl/verilog/spi_defines.v
spi/rtl/verilog/spi_shift.v
spi/rtl/verilog/spi_top.v
spi/rtl/verilog/timescale.v
spi/sim/
spi/sim/CVS/
spi/sim/CVS/Root
spi/sim/CVS/Repository
spi/sim/CVS/Entries
spi/sim/rtl_sim/
spi/sim/rtl_sim/CVS/
spi/sim/rtl_sim/CVS/Root
spi/sim/rtl_sim/CVS/Repository
spi/sim/rtl_sim/CVS/Entries
spi/sim/rtl_sim/run/
spi/sim/rtl_sim/run/CVS/
spi/sim/rtl_sim/run/CVS/Root
spi/sim/rtl_sim/run/CVS/Repository
spi/sim/rtl_sim/run/CVS/Entries
spi/sim/rtl_sim/run/rtl.fl
spi/sim/rtl_sim/run/run_sim
spi/sim/rtl_sim/run/sim.fl
spi/sim/run/
spi/sim/run/CVS/
spi/sim/run/CVS/Root
spi/sim/run/CVS/Repository
spi/sim/run/CVS/Entries