文件名称:cic_cq
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- 上传时间:2014-06-11
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文件大小:1.13mb
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在altera平台用verilog硬件描述语言实现cic抽取滤波,包含完整的工程代码,已经仿真通过,可以直接用于实践-In the Altera platform using Verilog hardware descr iption language CIC decimation filter, contains the complete project code, has been adopted by simulation, can be used directly in practice
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下载文件列表
cic_cq/
cic_cq/derivative_filter/
cic_cq/derivative_filter/data_generate.v
cic_cq/derivative_filter/der_filter_27sub.v
cic_cq/derivative_filter/derivative_filter.v
cic_cq/derivative_filter/derivative_filter_tb.v
cic_cq/pro/
cic_cq/scr/
cic_cq/scr/cic/
cic_cq/scr/cic/pro/
cic_cq/scr/cic/scr/
cic_cq/scr/cic/scr/CIC抽取滤波器.doc
cic_cq/scr/cic/scr/CIC抽取滤波器.docx
cic_cq/scr/cic/scr/cic.cr.mti
cic_cq/scr/cic/scr/cic.mpf
cic_cq/scr/cic/scr/cic_dec24.v
cic_cq/scr/cic/scr/cic_dec_arithmetic.v
cic_cq/scr/cic/scr/der_filter_27sub.v
cic_cq/scr/cic/scr/derivative_filter.v
cic_cq/scr/cic/scr/derivative_filter.v.bak
cic_cq/scr/cic/scr/fir_analyz_out_data.m
cic_cq/scr/cic/scr/fir_analyz_signal_data.m
cic_cq/scr/cic/scr/monopole_integrator_first.v
cic_cq/scr/cic/scr/multilevel_der_filter.v
cic_cq/scr/cic/scr/multilevel_integrator.v
cic_cq/scr/cic/scr/out_data.dat
cic_cq/scr/cic/scr/quantization.m
cic_cq/scr/cic/scr/signal_1m.dat
cic_cq/scr/cic/scr/signal_1m.dat.bak
cic_cq/scr/cic/scr/signal_data.dat
cic_cq/scr/cic/scr/signal_gen0.v
cic_cq/scr/cic/scr/signal_gen0.v.bak
cic_cq/scr/cic/scr/sin_1MHz_gen.m
cic_cq/scr/cic/scr/tb_cic.v
cic_cq/scr/cic/scr/vsim.wlf
cic_cq/scr/cic/scr/work/
cic_cq/scr/cic/scr/work/_info
cic_cq/scr/cic/scr/work/_temp/
cic_cq/scr/cic/scr/work/_vmake
cic_cq/scr/cic/scr/work/cic_dec24/
cic_cq/scr/cic/scr/work/cic_dec24/_primary.dat
cic_cq/scr/cic/scr/work/cic_dec24/_primary.dbs
cic_cq/scr/cic/scr/work/cic_dec24/_primary.vhd
cic_cq/scr/cic/scr/work/cic_dec24/verilog.asm
cic_cq/scr/cic/scr/work/cic_dec24/verilog.rw
cic_cq/scr/cic/scr/work/cic_dec_arithmetic/
cic_cq/scr/cic/scr/work/cic_dec_arithmetic/_primary.dat
cic_cq/scr/cic/scr/work/cic_dec_arithmetic/_primary.dbs
cic_cq/scr/cic/scr/work/cic_dec_arithmetic/_primary.vhd
cic_cq/scr/cic/scr/work/cic_dec_arithmetic/verilog.asm
cic_cq/scr/cic/scr/work/cic_dec_arithmetic/verilog.rw
cic_cq/scr/cic/scr/work/der_filter_27sub/
cic_cq/scr/cic/scr/work/der_filter_27sub/_primary.dat
cic_cq/scr/cic/scr/work/der_filter_27sub/_primary.dbs
cic_cq/scr/cic/scr/work/der_filter_27sub/_primary.vhd
cic_cq/scr/cic/scr/work/der_filter_27sub/verilog.asm
cic_cq/scr/cic/scr/work/der_filter_27sub/verilog.rw
cic_cq/scr/cic/scr/work/derivative_filter/
cic_cq/scr/cic/scr/work/derivative_filter/_primary.dat
cic_cq/scr/cic/scr/work/derivative_filter/_primary.dbs
cic_cq/scr/cic/scr/work/derivative_filter/_primary.vhd
cic_cq/scr/cic/scr/work/derivative_filter/verilog.asm
cic_cq/scr/cic/scr/work/derivative_filter/verilog.rw
cic_cq/scr/cic/scr/work/monopole_integrator_first/
cic_cq/scr/cic/scr/work/monopole_integrator_first/_primary.dat
cic_cq/scr/cic/scr/work/monopole_integrator_first/_primary.dbs
cic_cq/scr/cic/scr/work/monopole_integrator_first/_primary.vhd
cic_cq/scr/cic/scr/work/monopole_integrator_first/verilog.asm
cic_cq/scr/cic/scr/work/monopole_integrator_first/verilog.rw
cic_cq/scr/cic/scr/work/multilevel_der_filter/
cic_cq/scr/cic/scr/work/multilevel_der_filter/_primary.dat
cic_cq/scr/cic/scr/work/multilevel_der_filter/_primary.dbs
cic_cq/scr/cic/scr/work/multilevel_der_filter/_primary.vhd
cic_cq/scr/cic/scr/work/multilevel_der_filter/verilog.asm
cic_cq/scr/cic/scr/work/multilevel_der_filter/verilog.rw
cic_cq/scr/cic/scr/work/multilevel_integrator/
cic_cq/scr/cic/scr/work/multilevel_integrator/_primary.dat
cic_cq/scr/cic/scr/work/multilevel_integrator/_primary.dbs
cic_cq/scr/cic/scr/work/multilevel_integrator/_primary.vhd
cic_cq/scr/cic/scr/work/multilevel_integrator/verilog.asm
cic_cq/scr/cic/scr/work/multilevel_integrator/verilog.rw
cic_cq/scr/cic/scr/work/signal_gen0/
cic_cq/scr/cic/scr/work/signal_gen0/_primary.dat
cic_cq/scr/cic/scr/work/signal_gen0/_primary.dbs
cic_cq/scr/cic/scr/work/signal_gen0/_primary.vhd
cic_cq/scr/cic/scr/work/signal_gen0/verilog.asm
cic_cq/scr/cic/scr/work/signal_gen0/verilog.rw
cic_cq/scr/cic/scr/work/tb_cic/
cic_cq/scr/cic/scr/work/tb_cic/_primary.dat
cic_cq/scr/cic/scr/work/tb_cic/_primary.dbs
cic_cq/scr/cic/scr/work/tb_cic/_primary.vhd
cic_cq/scr/cic/scr/work/tb_cic/verilog.asm
cic_cq/scr/cic/scr/work/tb_cic/verilog.rw
cic_cq/scr/cic/scr/~$$新建 Microsoft Visio Drawing.~vsdx
cic_cq/scr/cic/scr/无标题.png
cic_cq/scr/cic/scr/滤波器操作说明.doc
cic_cq/scr/cic/sim/
cic_cq/scr/cic/sim/cic.cr.mti
cic_cq/scr/cic/sim/cic.mpf
cic_cq/scr/cic/sim/out_data.dat
cic_cq/scr/cic/sim/signal_data.dat
cic_cq/scr/cic/sim/vsim.wlf
cic_cq/scr/cic/sim/work/
cic_cq/scr/cic/sim/work/_info
cic_cq/scr/cic/sim/work/_temp/
cic_cq/scr/cic/sim/work/_vmake
cic_cq/scr/cic/sim/work/cic_dec24/
cic_cq/scr/cic/sim/work/cic_dec24/_primary.dat
cic_cq/scr/cic/sim/work/cic_dec24/_primary.dbs
cic_cq/scr/cic/sim/work/cic_dec24/_primary.vhd
cic_cq/scr/cic/sim/work/cic_dec24/verilog.asm
cic_cq/scr/cic/sim/work/cic_dec24/verilog.rw
cic_cq/scr/cic/sim/work/cic_dec_arithmetic/
cic_cq/scr/cic/sim/work/cic_dec_arithmetic/_primary.dat
cic_cq/scr/cic/sim/work/cic_dec_arithmetic/_primary.dbs
cic_cq/scr/cic/sim/work/cic_dec_arithmetic/_primary.vhd
cic_cq/scr/cic/sim/work/cic_dec_arithmetic/verilog.asm
cic_cq/scr/cic/sim/work/cic_dec_arithmetic/verilog.rw
cic_cq/scr/cic/sim/work/der_filter_27sub/
cic_cq/scr/cic/sim/work/der_filter_2
cic_cq/derivative_filter/
cic_cq/derivative_filter/data_generate.v
cic_cq/derivative_filter/der_filter_27sub.v
cic_cq/derivative_filter/derivative_filter.v
cic_cq/derivative_filter/derivative_filter_tb.v
cic_cq/pro/
cic_cq/scr/
cic_cq/scr/cic/
cic_cq/scr/cic/pro/
cic_cq/scr/cic/scr/
cic_cq/scr/cic/scr/CIC抽取滤波器.doc
cic_cq/scr/cic/scr/CIC抽取滤波器.docx
cic_cq/scr/cic/scr/cic.cr.mti
cic_cq/scr/cic/scr/cic.mpf
cic_cq/scr/cic/scr/cic_dec24.v
cic_cq/scr/cic/scr/cic_dec_arithmetic.v
cic_cq/scr/cic/scr/der_filter_27sub.v
cic_cq/scr/cic/scr/derivative_filter.v
cic_cq/scr/cic/scr/derivative_filter.v.bak
cic_cq/scr/cic/scr/fir_analyz_out_data.m
cic_cq/scr/cic/scr/fir_analyz_signal_data.m
cic_cq/scr/cic/scr/monopole_integrator_first.v
cic_cq/scr/cic/scr/multilevel_der_filter.v
cic_cq/scr/cic/scr/multilevel_integrator.v
cic_cq/scr/cic/scr/out_data.dat
cic_cq/scr/cic/scr/quantization.m
cic_cq/scr/cic/scr/signal_1m.dat
cic_cq/scr/cic/scr/signal_1m.dat.bak
cic_cq/scr/cic/scr/signal_data.dat
cic_cq/scr/cic/scr/signal_gen0.v
cic_cq/scr/cic/scr/signal_gen0.v.bak
cic_cq/scr/cic/scr/sin_1MHz_gen.m
cic_cq/scr/cic/scr/tb_cic.v
cic_cq/scr/cic/scr/vsim.wlf
cic_cq/scr/cic/scr/work/
cic_cq/scr/cic/scr/work/_info
cic_cq/scr/cic/scr/work/_temp/
cic_cq/scr/cic/scr/work/_vmake
cic_cq/scr/cic/scr/work/cic_dec24/
cic_cq/scr/cic/scr/work/cic_dec24/_primary.dat
cic_cq/scr/cic/scr/work/cic_dec24/_primary.dbs
cic_cq/scr/cic/scr/work/cic_dec24/_primary.vhd
cic_cq/scr/cic/scr/work/cic_dec24/verilog.asm
cic_cq/scr/cic/scr/work/cic_dec24/verilog.rw
cic_cq/scr/cic/scr/work/cic_dec_arithmetic/
cic_cq/scr/cic/scr/work/cic_dec_arithmetic/_primary.dat
cic_cq/scr/cic/scr/work/cic_dec_arithmetic/_primary.dbs
cic_cq/scr/cic/scr/work/cic_dec_arithmetic/_primary.vhd
cic_cq/scr/cic/scr/work/cic_dec_arithmetic/verilog.asm
cic_cq/scr/cic/scr/work/cic_dec_arithmetic/verilog.rw
cic_cq/scr/cic/scr/work/der_filter_27sub/
cic_cq/scr/cic/scr/work/der_filter_27sub/_primary.dat
cic_cq/scr/cic/scr/work/der_filter_27sub/_primary.dbs
cic_cq/scr/cic/scr/work/der_filter_27sub/_primary.vhd
cic_cq/scr/cic/scr/work/der_filter_27sub/verilog.asm
cic_cq/scr/cic/scr/work/der_filter_27sub/verilog.rw
cic_cq/scr/cic/scr/work/derivative_filter/
cic_cq/scr/cic/scr/work/derivative_filter/_primary.dat
cic_cq/scr/cic/scr/work/derivative_filter/_primary.dbs
cic_cq/scr/cic/scr/work/derivative_filter/_primary.vhd
cic_cq/scr/cic/scr/work/derivative_filter/verilog.asm
cic_cq/scr/cic/scr/work/derivative_filter/verilog.rw
cic_cq/scr/cic/scr/work/monopole_integrator_first/
cic_cq/scr/cic/scr/work/monopole_integrator_first/_primary.dat
cic_cq/scr/cic/scr/work/monopole_integrator_first/_primary.dbs
cic_cq/scr/cic/scr/work/monopole_integrator_first/_primary.vhd
cic_cq/scr/cic/scr/work/monopole_integrator_first/verilog.asm
cic_cq/scr/cic/scr/work/monopole_integrator_first/verilog.rw
cic_cq/scr/cic/scr/work/multilevel_der_filter/
cic_cq/scr/cic/scr/work/multilevel_der_filter/_primary.dat
cic_cq/scr/cic/scr/work/multilevel_der_filter/_primary.dbs
cic_cq/scr/cic/scr/work/multilevel_der_filter/_primary.vhd
cic_cq/scr/cic/scr/work/multilevel_der_filter/verilog.asm
cic_cq/scr/cic/scr/work/multilevel_der_filter/verilog.rw
cic_cq/scr/cic/scr/work/multilevel_integrator/
cic_cq/scr/cic/scr/work/multilevel_integrator/_primary.dat
cic_cq/scr/cic/scr/work/multilevel_integrator/_primary.dbs
cic_cq/scr/cic/scr/work/multilevel_integrator/_primary.vhd
cic_cq/scr/cic/scr/work/multilevel_integrator/verilog.asm
cic_cq/scr/cic/scr/work/multilevel_integrator/verilog.rw
cic_cq/scr/cic/scr/work/signal_gen0/
cic_cq/scr/cic/scr/work/signal_gen0/_primary.dat
cic_cq/scr/cic/scr/work/signal_gen0/_primary.dbs
cic_cq/scr/cic/scr/work/signal_gen0/_primary.vhd
cic_cq/scr/cic/scr/work/signal_gen0/verilog.asm
cic_cq/scr/cic/scr/work/signal_gen0/verilog.rw
cic_cq/scr/cic/scr/work/tb_cic/
cic_cq/scr/cic/scr/work/tb_cic/_primary.dat
cic_cq/scr/cic/scr/work/tb_cic/_primary.dbs
cic_cq/scr/cic/scr/work/tb_cic/_primary.vhd
cic_cq/scr/cic/scr/work/tb_cic/verilog.asm
cic_cq/scr/cic/scr/work/tb_cic/verilog.rw
cic_cq/scr/cic/scr/~$$新建 Microsoft Visio Drawing.~vsdx
cic_cq/scr/cic/scr/无标题.png
cic_cq/scr/cic/scr/滤波器操作说明.doc
cic_cq/scr/cic/sim/
cic_cq/scr/cic/sim/cic.cr.mti
cic_cq/scr/cic/sim/cic.mpf
cic_cq/scr/cic/sim/out_data.dat
cic_cq/scr/cic/sim/signal_data.dat
cic_cq/scr/cic/sim/vsim.wlf
cic_cq/scr/cic/sim/work/
cic_cq/scr/cic/sim/work/_info
cic_cq/scr/cic/sim/work/_temp/
cic_cq/scr/cic/sim/work/_vmake
cic_cq/scr/cic/sim/work/cic_dec24/
cic_cq/scr/cic/sim/work/cic_dec24/_primary.dat
cic_cq/scr/cic/sim/work/cic_dec24/_primary.dbs
cic_cq/scr/cic/sim/work/cic_dec24/_primary.vhd
cic_cq/scr/cic/sim/work/cic_dec24/verilog.asm
cic_cq/scr/cic/sim/work/cic_dec24/verilog.rw
cic_cq/scr/cic/sim/work/cic_dec_arithmetic/
cic_cq/scr/cic/sim/work/cic_dec_arithmetic/_primary.dat
cic_cq/scr/cic/sim/work/cic_dec_arithmetic/_primary.dbs
cic_cq/scr/cic/sim/work/cic_dec_arithmetic/_primary.vhd
cic_cq/scr/cic/sim/work/cic_dec_arithmetic/verilog.asm
cic_cq/scr/cic/sim/work/cic_dec_arithmetic/verilog.rw
cic_cq/scr/cic/sim/work/der_filter_27sub/
cic_cq/scr/cic/sim/work/der_filter_2
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