文件名称:cic_cz
-
所属分类:
- 标签属性:
- 上传时间:2014-06-11
-
文件大小:1.04mb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
在altera平台用verilog硬件描述语言实现cic插值滤波,在modelsim软件中仿真通过,包含完整的工程代码,可以直接下载到FPGA中运行-In the Altera platform using Verilog hardware descr iption language CIC interpolation filter, through the simulation in Modelsim software, including the complete project code, can be directly downloaded to the FPGA operation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
cic_cz/
cic_cz/pro/
cic_cz/scr/
cic_cz/scr/CIC插值滤波器.doc
cic_cz/scr/CIC插值滤波器.docx
cic_cz/scr/cic.cr.mti
cic_cz/scr/cic.mpf
cic_cz/scr/cic_interp24.v
cic_cz/scr/cic_interp_arithmetic.v
cic_cz/scr/derivative_filter.v
cic_cz/scr/fir_analyz_out_data.m
cic_cz/scr/fir_analyz_signal_data.m
cic_cz/scr/monopole_integrator_first.v
cic_cz/scr/multilevel_der_filter.v
cic_cz/scr/multilevel_integrator.v
cic_cz/scr/out_data.dat
cic_cz/scr/signal_1m.dat
cic_cz/scr/signal_data.dat
cic_cz/scr/signal_gen0.v
cic_cz/scr/sin_gen.m
cic_cz/scr/tb_cic.v
cic_cz/scr/vsim.wlf
cic_cz/scr/work/
cic_cz/scr/work/_info
cic_cz/scr/work/_temp/
cic_cz/scr/work/_temp/vlogkdkhyi
cic_cz/scr/work/_temp/vlogrqi595
cic_cz/scr/work/_vmake
cic_cz/scr/work/cic_interp24/
cic_cz/scr/work/cic_interp24/_primary.dat
cic_cz/scr/work/cic_interp24/_primary.dbs
cic_cz/scr/work/cic_interp24/_primary.vhd
cic_cz/scr/work/cic_interp24/verilog.asm
cic_cz/scr/work/cic_interp24/verilog.rw
cic_cz/scr/work/cic_interp_arithmetic/
cic_cz/scr/work/cic_interp_arithmetic/_primary.dat
cic_cz/scr/work/cic_interp_arithmetic/_primary.dbs
cic_cz/scr/work/cic_interp_arithmetic/_primary.vhd
cic_cz/scr/work/cic_interp_arithmetic/verilog.asm
cic_cz/scr/work/cic_interp_arithmetic/verilog.rw
cic_cz/scr/work/derivative_filter/
cic_cz/scr/work/derivative_filter/_primary.dat
cic_cz/scr/work/derivative_filter/_primary.dbs
cic_cz/scr/work/derivative_filter/_primary.vhd
cic_cz/scr/work/derivative_filter/verilog.asm
cic_cz/scr/work/derivative_filter/verilog.rw
cic_cz/scr/work/monopole_integrator_first/
cic_cz/scr/work/monopole_integrator_first/_primary.dat
cic_cz/scr/work/monopole_integrator_first/_primary.dbs
cic_cz/scr/work/monopole_integrator_first/_primary.vhd
cic_cz/scr/work/monopole_integrator_first/verilog.asm
cic_cz/scr/work/monopole_integrator_first/verilog.rw
cic_cz/scr/work/multilevel_der_filter/
cic_cz/scr/work/multilevel_der_filter/_primary.dat
cic_cz/scr/work/multilevel_der_filter/_primary.dbs
cic_cz/scr/work/multilevel_der_filter/_primary.vhd
cic_cz/scr/work/multilevel_der_filter/verilog.asm
cic_cz/scr/work/multilevel_der_filter/verilog.rw
cic_cz/scr/work/multilevel_integrator/
cic_cz/scr/work/multilevel_integrator/_primary.dat
cic_cz/scr/work/multilevel_integrator/_primary.dbs
cic_cz/scr/work/multilevel_integrator/_primary.vhd
cic_cz/scr/work/multilevel_integrator/verilog.asm
cic_cz/scr/work/multilevel_integrator/verilog.rw
cic_cz/scr/work/signal_gen0/
cic_cz/scr/work/signal_gen0/_primary.dat
cic_cz/scr/work/signal_gen0/_primary.dbs
cic_cz/scr/work/signal_gen0/_primary.vhd
cic_cz/scr/work/signal_gen0/verilog.asm
cic_cz/scr/work/signal_gen0/verilog.rw
cic_cz/scr/work/tb_cic/
cic_cz/scr/work/tb_cic/_primary.dat
cic_cz/scr/work/tb_cic/_primary.dbs
cic_cz/scr/work/tb_cic/_primary.vhd
cic_cz/scr/work/tb_cic/verilog.asm
cic_cz/scr/work/tb_cic/verilog.rw
cic_cz/scr/无标题.png
cic_cz/scr/滤波器操作说明(抽取和插值).doc
cic_cz/scr/滤波器操作说明.doc
cic_cz/scr/第八章__信号的抽取与插值.pdf
cic_cz/sim/
cic_cz/pro/
cic_cz/scr/
cic_cz/scr/CIC插值滤波器.doc
cic_cz/scr/CIC插值滤波器.docx
cic_cz/scr/cic.cr.mti
cic_cz/scr/cic.mpf
cic_cz/scr/cic_interp24.v
cic_cz/scr/cic_interp_arithmetic.v
cic_cz/scr/derivative_filter.v
cic_cz/scr/fir_analyz_out_data.m
cic_cz/scr/fir_analyz_signal_data.m
cic_cz/scr/monopole_integrator_first.v
cic_cz/scr/multilevel_der_filter.v
cic_cz/scr/multilevel_integrator.v
cic_cz/scr/out_data.dat
cic_cz/scr/signal_1m.dat
cic_cz/scr/signal_data.dat
cic_cz/scr/signal_gen0.v
cic_cz/scr/sin_gen.m
cic_cz/scr/tb_cic.v
cic_cz/scr/vsim.wlf
cic_cz/scr/work/
cic_cz/scr/work/_info
cic_cz/scr/work/_temp/
cic_cz/scr/work/_temp/vlogkdkhyi
cic_cz/scr/work/_temp/vlogrqi595
cic_cz/scr/work/_vmake
cic_cz/scr/work/cic_interp24/
cic_cz/scr/work/cic_interp24/_primary.dat
cic_cz/scr/work/cic_interp24/_primary.dbs
cic_cz/scr/work/cic_interp24/_primary.vhd
cic_cz/scr/work/cic_interp24/verilog.asm
cic_cz/scr/work/cic_interp24/verilog.rw
cic_cz/scr/work/cic_interp_arithmetic/
cic_cz/scr/work/cic_interp_arithmetic/_primary.dat
cic_cz/scr/work/cic_interp_arithmetic/_primary.dbs
cic_cz/scr/work/cic_interp_arithmetic/_primary.vhd
cic_cz/scr/work/cic_interp_arithmetic/verilog.asm
cic_cz/scr/work/cic_interp_arithmetic/verilog.rw
cic_cz/scr/work/derivative_filter/
cic_cz/scr/work/derivative_filter/_primary.dat
cic_cz/scr/work/derivative_filter/_primary.dbs
cic_cz/scr/work/derivative_filter/_primary.vhd
cic_cz/scr/work/derivative_filter/verilog.asm
cic_cz/scr/work/derivative_filter/verilog.rw
cic_cz/scr/work/monopole_integrator_first/
cic_cz/scr/work/monopole_integrator_first/_primary.dat
cic_cz/scr/work/monopole_integrator_first/_primary.dbs
cic_cz/scr/work/monopole_integrator_first/_primary.vhd
cic_cz/scr/work/monopole_integrator_first/verilog.asm
cic_cz/scr/work/monopole_integrator_first/verilog.rw
cic_cz/scr/work/multilevel_der_filter/
cic_cz/scr/work/multilevel_der_filter/_primary.dat
cic_cz/scr/work/multilevel_der_filter/_primary.dbs
cic_cz/scr/work/multilevel_der_filter/_primary.vhd
cic_cz/scr/work/multilevel_der_filter/verilog.asm
cic_cz/scr/work/multilevel_der_filter/verilog.rw
cic_cz/scr/work/multilevel_integrator/
cic_cz/scr/work/multilevel_integrator/_primary.dat
cic_cz/scr/work/multilevel_integrator/_primary.dbs
cic_cz/scr/work/multilevel_integrator/_primary.vhd
cic_cz/scr/work/multilevel_integrator/verilog.asm
cic_cz/scr/work/multilevel_integrator/verilog.rw
cic_cz/scr/work/signal_gen0/
cic_cz/scr/work/signal_gen0/_primary.dat
cic_cz/scr/work/signal_gen0/_primary.dbs
cic_cz/scr/work/signal_gen0/_primary.vhd
cic_cz/scr/work/signal_gen0/verilog.asm
cic_cz/scr/work/signal_gen0/verilog.rw
cic_cz/scr/work/tb_cic/
cic_cz/scr/work/tb_cic/_primary.dat
cic_cz/scr/work/tb_cic/_primary.dbs
cic_cz/scr/work/tb_cic/_primary.vhd
cic_cz/scr/work/tb_cic/verilog.asm
cic_cz/scr/work/tb_cic/verilog.rw
cic_cz/scr/无标题.png
cic_cz/scr/滤波器操作说明(抽取和插值).doc
cic_cz/scr/滤波器操作说明.doc
cic_cz/scr/第八章__信号的抽取与插值.pdf
cic_cz/sim/
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.