文件名称:adc_test
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- 上传时间:2014-06-13
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文件大小:4.38mb
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已下载:0次
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介绍说明--下载内容来自于网络,使用问题请自行百度
verilog AD采样源代码,包括test代码-verilog AD
(系统自动生成,下载前可以参看下载内容)
下载文件列表
eetop.cn_adc_test/adc_test/adc_test.prj
eetop.cn_adc_test/adc_test/designer/impl1/adc_ram_0.ide_des
eetop.cn_adc_test/adc_test/designer/impl1/adc_sample.ide_des
eetop.cn_adc_test/adc_test/designer/impl1/testbench.ide_des
eetop.cn_adc_test/adc_test/designer/impl1/top.ide_des
eetop.cn_adc_test/adc_test/hdl/adc_sample.v
eetop.cn_adc_test/adc_test/hdl/adc_sample.v.bak
eetop.cn_adc_test/adc_test/hdl/top.v
eetop.cn_adc_test/adc_test/simulation/adc_ram_0_R0C0.mem
eetop.cn_adc_test/adc_test/simulation/adc_ram_0_R0C1.mem
eetop.cn_adc_test/adc_test/simulation/modelsim.ini
eetop.cn_adc_test/adc_test/simulation/modelsim.ini.sav
eetop.cn_adc_test/adc_test/simulation/modelsim.log
eetop.cn_adc_test/adc_test/simulation/presynth/adc_ram_0/verilog.psm
eetop.cn_adc_test/adc_test/simulation/presynth/adc_ram_0/_primary.dat
eetop.cn_adc_test/adc_test/simulation/presynth/adc_ram_0/_primary.dbs
eetop.cn_adc_test/adc_test/simulation/presynth/adc_ram_0/_primary.vhd
eetop.cn_adc_test/adc_test/simulation/presynth/adc_sample/verilog.psm
eetop.cn_adc_test/adc_test/simulation/presynth/adc_sample/_primary.dat
eetop.cn_adc_test/adc_test/simulation/presynth/adc_sample/_primary.dbs
eetop.cn_adc_test/adc_test/simulation/presynth/adc_sample/_primary.vhd
eetop.cn_adc_test/adc_test/simulation/presynth/testbench/verilog.psm
eetop.cn_adc_test/adc_test/simulation/presynth/testbench/_primary.dat
eetop.cn_adc_test/adc_test/simulation/presynth/testbench/_primary.dbs
eetop.cn_adc_test/adc_test/simulation/presynth/testbench/_primary.vhd
eetop.cn_adc_test/adc_test/simulation/presynth/top/verilog.psm
eetop.cn_adc_test/adc_test/simulation/presynth/top/_primary.dat
eetop.cn_adc_test/adc_test/simulation/presynth/top/_primary.dbs
eetop.cn_adc_test/adc_test/simulation/presynth/top/_primary.vhd
eetop.cn_adc_test/adc_test/simulation/presynth/_info
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlog195mb2
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlog1dg5bx
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlog1syggc
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlog9grrd4
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogacidrb
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogbr9d69
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogcfie2e
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogfqr9zz
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogxa3nbq
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogyhwy28
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogzb918e
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogzxbbwy
eetop.cn_adc_test/adc_test/simulation/presynth/_vmake
eetop.cn_adc_test/adc_test/simulation/run.do
eetop.cn_adc_test/adc_test/simulation/vsim.wlf
eetop.cn_adc_test/adc_test/simulation/wave.do
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0.cxf
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0.gen
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0.log
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0.shx
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0.v
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0_R0C0.mem
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0_R0C1.mem
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0_work.ixf
eetop.cn_adc_test/adc_test/smartgen/smartgen.aws
eetop.cn_adc_test/adc_test/stimulus/testbench.v
eetop.cn_adc_test/adc_test/stimulus/testbench.v.bak
eetop.cn_adc_test/adc_test/synthesis/.recordref
eetop.cn_adc_test/adc_test/synthesis/adc_sample.areasrr
eetop.cn_adc_test/adc_test/synthesis/adc_sample.edn
eetop.cn_adc_test/adc_test/synthesis/adc_sample.map
eetop.cn_adc_test/adc_test/synthesis/adc_sample.pdc
eetop.cn_adc_test/adc_test/synthesis/adc_sample.sdf
eetop.cn_adc_test/adc_test/synthesis/adc_sample.so
eetop.cn_adc_test/adc_test/synthesis/adc_sample.srd
eetop.cn_adc_test/adc_test/synthesis/adc_sample.srm
eetop.cn_adc_test/adc_test/synthesis/adc_sample.srr
eetop.cn_adc_test/adc_test/synthesis/adc_sample.srs
eetop.cn_adc_test/adc_test/synthesis/adc_sample.szr
eetop.cn_adc_test/adc_test/synthesis/adc_sample.tlg
eetop.cn_adc_test/adc_test/synthesis/adc_sample_sdc.sdc
eetop.cn_adc_test/adc_test/synthesis/adc_sample_syn.prj
eetop.cn_adc_test/adc_test/synthesis/backup/adc_sample.srr
eetop.cn_adc_test/adc_test/synthesis/backup/top.srr
eetop.cn_adc_test/adc_test/synthesis/run_options.txt
eetop.cn_adc_test/adc_test/synthesis/stdout.log
eetop.cn_adc_test/adc_test/synthesis/syntmp/adc_sample.plg
eetop.cn_adc_test/adc_test/synthesis/syntmp/top.plg
eetop.cn_adc_test/adc_test/synthesis/top.areasrr
eetop.cn_adc_test/adc_test/synthesis/top.edn
eetop.cn_adc_test/adc_test/synthesis/top.map
eetop.cn_adc_test/adc_test/synthesis/top.pdc
eetop.cn_adc_test/adc_test/synthesis/top.sdf
eetop.cn_adc_test/adc_test/synthesis/top.so
eetop.cn_adc_test/adc_test/synthesis/top.srd
eetop.cn_adc_test/adc_test/synthesis/top.srm
eetop.cn_adc_test/adc_test/synthesis/top.srr
eetop.cn_adc_test/adc_test/synthesis/top.srs
eetop.cn_adc_test/adc_test/synthesis/top.szr
eetop.cn_adc_test/adc_test/synthesis/top.tlg
eetop.cn_adc_test/adc_test/synthesis/top_sdc.sdc
ee
eetop.cn_adc_test/adc_test/designer/impl1/adc_ram_0.ide_des
eetop.cn_adc_test/adc_test/designer/impl1/adc_sample.ide_des
eetop.cn_adc_test/adc_test/designer/impl1/testbench.ide_des
eetop.cn_adc_test/adc_test/designer/impl1/top.ide_des
eetop.cn_adc_test/adc_test/hdl/adc_sample.v
eetop.cn_adc_test/adc_test/hdl/adc_sample.v.bak
eetop.cn_adc_test/adc_test/hdl/top.v
eetop.cn_adc_test/adc_test/simulation/adc_ram_0_R0C0.mem
eetop.cn_adc_test/adc_test/simulation/adc_ram_0_R0C1.mem
eetop.cn_adc_test/adc_test/simulation/modelsim.ini
eetop.cn_adc_test/adc_test/simulation/modelsim.ini.sav
eetop.cn_adc_test/adc_test/simulation/modelsim.log
eetop.cn_adc_test/adc_test/simulation/presynth/adc_ram_0/verilog.psm
eetop.cn_adc_test/adc_test/simulation/presynth/adc_ram_0/_primary.dat
eetop.cn_adc_test/adc_test/simulation/presynth/adc_ram_0/_primary.dbs
eetop.cn_adc_test/adc_test/simulation/presynth/adc_ram_0/_primary.vhd
eetop.cn_adc_test/adc_test/simulation/presynth/adc_sample/verilog.psm
eetop.cn_adc_test/adc_test/simulation/presynth/adc_sample/_primary.dat
eetop.cn_adc_test/adc_test/simulation/presynth/adc_sample/_primary.dbs
eetop.cn_adc_test/adc_test/simulation/presynth/adc_sample/_primary.vhd
eetop.cn_adc_test/adc_test/simulation/presynth/testbench/verilog.psm
eetop.cn_adc_test/adc_test/simulation/presynth/testbench/_primary.dat
eetop.cn_adc_test/adc_test/simulation/presynth/testbench/_primary.dbs
eetop.cn_adc_test/adc_test/simulation/presynth/testbench/_primary.vhd
eetop.cn_adc_test/adc_test/simulation/presynth/top/verilog.psm
eetop.cn_adc_test/adc_test/simulation/presynth/top/_primary.dat
eetop.cn_adc_test/adc_test/simulation/presynth/top/_primary.dbs
eetop.cn_adc_test/adc_test/simulation/presynth/top/_primary.vhd
eetop.cn_adc_test/adc_test/simulation/presynth/_info
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlog195mb2
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlog1dg5bx
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlog1syggc
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlog9grrd4
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogacidrb
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogbr9d69
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogcfie2e
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogfqr9zz
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogxa3nbq
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogyhwy28
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogzb918e
eetop.cn_adc_test/adc_test/simulation/presynth/_temp/vlogzxbbwy
eetop.cn_adc_test/adc_test/simulation/presynth/_vmake
eetop.cn_adc_test/adc_test/simulation/run.do
eetop.cn_adc_test/adc_test/simulation/vsim.wlf
eetop.cn_adc_test/adc_test/simulation/wave.do
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0.cxf
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0.gen
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0.log
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0.shx
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0.v
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0_R0C0.mem
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0/adc_ram_0_R0C1.mem
eetop.cn_adc_test/adc_test/smartgen/adc_ram_0_work.ixf
eetop.cn_adc_test/adc_test/smartgen/smartgen.aws
eetop.cn_adc_test/adc_test/stimulus/testbench.v
eetop.cn_adc_test/adc_test/stimulus/testbench.v.bak
eetop.cn_adc_test/adc_test/synthesis/.recordref
eetop.cn_adc_test/adc_test/synthesis/adc_sample.areasrr
eetop.cn_adc_test/adc_test/synthesis/adc_sample.edn
eetop.cn_adc_test/adc_test/synthesis/adc_sample.map
eetop.cn_adc_test/adc_test/synthesis/adc_sample.pdc
eetop.cn_adc_test/adc_test/synthesis/adc_sample.sdf
eetop.cn_adc_test/adc_test/synthesis/adc_sample.so
eetop.cn_adc_test/adc_test/synthesis/adc_sample.srd
eetop.cn_adc_test/adc_test/synthesis/adc_sample.srm
eetop.cn_adc_test/adc_test/synthesis/adc_sample.srr
eetop.cn_adc_test/adc_test/synthesis/adc_sample.srs
eetop.cn_adc_test/adc_test/synthesis/adc_sample.szr
eetop.cn_adc_test/adc_test/synthesis/adc_sample.tlg
eetop.cn_adc_test/adc_test/synthesis/adc_sample_sdc.sdc
eetop.cn_adc_test/adc_test/synthesis/adc_sample_syn.prj
eetop.cn_adc_test/adc_test/synthesis/backup/adc_sample.srr
eetop.cn_adc_test/adc_test/synthesis/backup/top.srr
eetop.cn_adc_test/adc_test/synthesis/run_options.txt
eetop.cn_adc_test/adc_test/synthesis/stdout.log
eetop.cn_adc_test/adc_test/synthesis/syntmp/adc_sample.plg
eetop.cn_adc_test/adc_test/synthesis/syntmp/top.plg
eetop.cn_adc_test/adc_test/synthesis/top.areasrr
eetop.cn_adc_test/adc_test/synthesis/top.edn
eetop.cn_adc_test/adc_test/synthesis/top.map
eetop.cn_adc_test/adc_test/synthesis/top.pdc
eetop.cn_adc_test/adc_test/synthesis/top.sdf
eetop.cn_adc_test/adc_test/synthesis/top.so
eetop.cn_adc_test/adc_test/synthesis/top.srd
eetop.cn_adc_test/adc_test/synthesis/top.srm
eetop.cn_adc_test/adc_test/synthesis/top.srr
eetop.cn_adc_test/adc_test/synthesis/top.srs
eetop.cn_adc_test/adc_test/synthesis/top.szr
eetop.cn_adc_test/adc_test/synthesis/top.tlg
eetop.cn_adc_test/adc_test/synthesis/top_sdc.sdc
ee
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