文件名称:LogicSynthesis2_CMOSBasics
-
所属分类：
- 标签属性：
- 上传时间：2014-07-07
-
文件大小：1.55mb
-
已下载：0次
-
提 供 者：
-
相关连接：无下载说明：别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容来自于网络，使用问题请自行百度
LogicSynthesis2_CMOSBasics
Key Problem: Timing assumption
during prelayout synthesis widely
differs from the post layout reality.
• This happens because the
interconnect delay dominates the
overall propagation delay in DSM
(Deep Sub‐Micron) technologies.
• As a result getting a timing closure
becomes a challenge-LogicSynthesis2_CMOSBasics
Key Problem: Timing assumption
during prelayout synthesis widely
differs from the post layout reality.
• This happens because the
interconnect delay dominates the
overall propagation delay in DSM
(Deep Sub‐Micron) technologies.
• As a result getting a timing closure
becomes a challenge
Key Problem: Timing assumption
during prelayout synthesis widely
differs from the post layout reality.
• This happens because the
interconnect delay dominates the
overall propagation delay in DSM
(Deep Sub‐Micron) technologies.
• As a result getting a timing closure
becomes a challenge-LogicSynthesis2_CMOSBasics
Key Problem: Timing assumption
during prelayout synthesis widely
differs from the post layout reality.
• This happens because the
interconnect delay dominates the
overall propagation delay in DSM
(Deep Sub‐Micron) technologies.
• As a result getting a timing closure
becomes a challenge
(系统自动生成,下载前可以参看下载内容)
下载文件列表
LogicSynthesis2_CMOSBasics.pdf
本网站为编程资源及源代码搜集、介绍的搜索网站，版权归原作者所有！ 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.